Announced today at OCP Summit, Cisco and Nvidia have partnered on the open USFP optical spec, alongside new Cisco Silicon One ASICs and runtime security to scale…
Announced today at OCP Summit, Cisco and Nvidia have partnered on the open USFP optical spec, alongside new Cisco Silicon One ASICs and runtime security to scale next-generation Ethernet AI fabrics.
The new QODN non-isolated Osprey bus converters offer high efficiency and compact footprints for demanding AI data center…
The new QODN non-isolated Osprey bus converters offer high efficiency and compact footprints for demanding AI data center and high-density compute applications.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
Designing compact AI sensor nodes forces signal integrity and thermal management to compete for limited PCB copper,…
Designing compact AI sensor nodes forces signal integrity and thermal management to compete for limited PCB copper, creating severe PDN and thermal bottlenecks.
The LSM6DSK320X and ISM6HGK256X combine low-g and high-g measurement in a 2.5 mm x 3 mm package using lead-free, BPA-free…
The LSM6DSK320X and ISM6HGK256X combine low-g and high-g measurement in a 2.5 mm x 3 mm package using lead-free, BPA-free materials.
In this interview article, Renesas VP Peter Jenkins discusses how the company is leveraging its automotive sensor…
In this interview article, Renesas VP Peter Jenkins discusses how the company is leveraging its automotive sensor heritage and mixed-signal ICs to power the future of edge AI and humanoid robotics.
The SY757xx family translates clock inputs from 1.2 to 3.3 V down to 1.2 V LVCMOS outputs at frequencies up to 250 MHz,
The SY757xx family translates clock inputs from 1.2 to 3.3 V down to 1.2 V LVCMOS outputs at frequencies up to 250 MHz,
The new PSOC Control C3 product line focuses on secure, high-performance power conversion and motor control applications.
The new PSOC Control C3 product line focuses on secure, high-performance power conversion and motor control applications.
Learn how EPC’s multi-stage ISOP architecture uses low-voltage GaN FETs to efficiently convert 800 V DC in AI data…
Learn how EPC’s multi-stage ISOP architecture uses low-voltage GaN FETs to efficiently convert 800 V DC in AI data centers, reducing output ripple and capacitance while achieving up to 98.5% efficiency.
Announced today by AtlasBase, Thalia is a 5.6B-well bio-silicon chip that uses synthetic DNA to break power and density…
Announced today by AtlasBase, Thalia is a 5.6B-well bio-silicon chip that uses synthetic DNA to break power and density bottlenecks in AI data center storage and molecular computing.
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring…
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring flagship AI performance to fanless Googlebooks.
By embedding heterogeneous Si, SiC, and GaN die directly into 12-inch silicon wafers with precision RDLs, Onsemi's EPP…
By embedding heterogeneous Si, SiC, and GaN die directly into 12-inch silicon wafers with precision RDLs, Onsemi's EPP replaces wire bonds and mold compounds to deliver up to 5x power density.
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end…
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end compute and proactive mobile intelligence.
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development…
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development platform, and a system-level reference architecture to eliminate tail latency, maximize power efficiency, and scale agentic AI clusters.
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power…
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power alternatives to boost efficiency and lower BoM costs.
The new evaluation kits aim to lower the barrier for on-device AI development with Alif’s AI/ML hardware-accelerated…
The new evaluation kits aim to lower the barrier for on-device AI development with Alif’s AI/ML hardware-accelerated Ensemble and Balletto MCUs.
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4…
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4 platform provide specialized architectures for agentic AI workloads across various domains.
Learn how MEMS sensor technology brings edge AI and vibration monitoring to smart manufacturing, enabling early defect…
Learn how MEMS sensor technology brings edge AI and vibration monitoring to smart manufacturing, enabling early defect detection and predictive maintenance to prevent downtime.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall…
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall Street financing to washing machines.
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