Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.
Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.
RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way…
RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way for integrating security features and more early in the development cycle.
In this exclusive Embedded World 2025 interview, we talk to AMD’s Kirk Saban about edge AI, ASICs vs. FPGAs, Adaptive…
In this exclusive Embedded World 2025 interview, we talk to AMD’s Kirk Saban about edge AI, ASICs vs. FPGAs, Adaptive SoCs, embedded x86, and the outlook ahead.
Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed…
Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed correctly, managed well, and backed with appropriate resources.
At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe.
At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe.
RISC-V “is changing the way people build every single computer,” says Mark Himelstein, the former CTO at RISC-V…
RISC-V “is changing the way people build every single computer,” says Mark Himelstein, the former CTO at RISC-V International. He joins us to explain the significance of the RISC-V ISA, open standard development challenges, and read poetry.
SiFive is helping lead the RISC-V revolution in automotive, Android, and AI. Senior VP Jack Kang joins the Moore’s…
SiFive is helping lead the RISC-V revolution in automotive, Android, and AI. Senior VP Jack Kang joins the Moore’s Lobby podcast to provide his insights on the success of SiFive and the open-standard RISC-V instruction set architecture (ISA).
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects…
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects to large-scale corporate initiatives.
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a…
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a hard-instantiated RISC-V core.
Adil Kidwai, VP and Head of Product Management at EdgeQ, discusses how they are aiming to redefine software-defined…
Adil Kidwai, VP and Head of Product Management at EdgeQ, discusses how they are aiming to redefine software-defined radios as they build what they believe is the world’s first base station-on-a-chip, using RISC-V to enable AI and 5G.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize”…
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize” artificial intelligence (AI).
SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.
SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.
With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.
With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.
The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.
The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.
With their collaboration, the firms hope to enable faster and improved functional verification testing for Bluespec’s…
With their collaboration, the firms hope to enable faster and improved functional verification testing for Bluespec’s RISC-V cores.
With the new processor, the company hopes to bring a feature-rich set of functions to the RISC-V community.
With the new processor, the company hopes to bring a feature-rich set of functions to the RISC-V community.
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