Latest Softcore Articles and Videos

A New Multimodal Architecture Said to Redefine the Way Transistors Work

Researchers at the University of Surrey have come up with a new type of transistor that offers linear behavior and huge upside.

November 02, 2020 by Jake Hertz

Ultrasound Receiver Architecture Undergoes a Seismic Shift

Ultrasound, with nearly a century of technological history, has seen its third major technological breakthrough coming out of North Carolina State.

August 20, 2020 by Adrian Gibbons

Architecture and Design Techniques of Op-Amps

In this video we will examine the internal circuitry of an operational amplifier. A thorough analysis of any professional-quality op-amp would be far too complicated for an introductory video tutorial, but if we focus on the overall architecture and a few specific design techniques, we can learn quite a bit about op-amp functionality without getting lost in the details.

August 02, 2020 by Robert Keim

SiFive, Co-Founder of RISC-V, Unveils Major Upgrades to RISC-V-Based Processors

As the co-founders of RISC-V, SiFive's level-up on processors could have significant implications for custom SoC design.

July 25, 2020 by Vanessa Samuel

The International Telecommunication Union Announces a New Architecture That Incorporates MI Mechanisms

Recently, a study into the architecture has been presented by members of the Wireless Networking and AI&ML research groups and described as a “new standard” for telecommunications networks.

May 21, 2020 by Luke James

COVID-19 Puts Spotlight on Open-Source RISC-V Cores, IP

Remote work during this pandemic has shed light anew on the virtues of RISC-V, which has just gotten more accessible.

May 20, 2020 by Antonio Anzaldua Jr.

Neural Network Architecture for a Python Implementation

This article discusses the Perceptron configuration that we will use for our experiments with neural-network training and classification, and we’ll also look at the related topic of bias nodes.

January 09, 2020 by Robert Keim

Microchip Announces First RISC-V-based SoC FPGA to Use Half the Power of Other FPGAs

Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.

December 10, 2019 by Lisa Boneta

AI Hardware Built from a Software-first Perspective: Groq’s Flexible Silicon Architecture

Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that offers inference solutions for AI acceleration.

December 03, 2019 by Majeed Ahmad

How RISC-V Security Stacks Strengthen Computer Architecture

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

November 26, 2019 by Ted Speers, Microchip

Learn About SAR ADCs: Architecture, Applications, and Support Circuitry

In this article, we’ll first review the basic architecture of a SAR ADC and then take a look at one of its common applications.

October 24, 2019 by Steve Arar

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

September 10, 2019 by Ted Marena, Western Digital

Alibaba’s Semiconductor Subsidiary Will Utilize Open-Source RISC-V Core

Alibaba is set to produce the next generation of Chinese processors with the RISC-V instead of Arm architecture.

July 29, 2019 by Robin Mitchell

Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

July 09, 2019 by Ted Marena, Western Digital

The Advanced Microcontroller Bus Architecture: An Introduction

This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.

June 02, 2019 by Stephen St. Michael

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

May 14, 2019 by Zvonimir Bandić, Western Digital

Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

April 16, 2019 by Greg Sullivan, Dover Microsystems

The Arm Architecture Explained

Learn more about the Arm computer architecture, including ISA, execution states, and processor families.

April 10, 2019 by Stephen St. Michael

Running Hard Real-Time Applications and Linux on PolarFire SoC

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

March 26, 2019 by Tim Morin, Microchip

What Is a Microcontroller? The Defining Characteristics and Architecture of a Common Component

In this article we’ll look at the defining characteristics of these extremely popular ICs, and then we’ll explore the internal architecture.

March 25, 2019 by Robert Keim

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