Solutions Disclosed at RISC-V Summit: Security, Verification, and More
At this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and software-defined SoCs.
This week is the annual RISC-V Summit in San Jose, CA, where many of the major players in the industry get together to share technology and discuss the future of the RISC-V industry. Building off of the moment of the numerous RISC-V announcements in 2022, this year’s summit has had no shortage of exciting announcements.
Among these, recent announcements from Imperas, XMOS, and Codasip have been of particular interest. In this article, we’ll examine each of these releases to understand the current and future direction of the RISC-V industry.
Imperas RISC-V Verification Tool Updates
The first set of news coming from this week’s RISC-V summit comes from Imperas regarding its RISC-V verification software.
Design verification is particularly important in RISC-V since the open-sourced nature of the standard means that anyone can contribute to IP. Hence, there is the potential for errors or inconsistencies to be introduced into the design if it is not carefully managed.
RISC-V design workflow with ImperasDV. Image used courtesy of Imperas
To address this, Imperas has announced a new set of updates to its ImperasDV software, which is a leading RISC-V design verification software tool. Amongst these updates includes the inclusion of riscvISACOV IP extensions, which is a set of SystemVerilog functional libraries, as well as the inclusion of architectural validation test suites.
These new test suites include RV32E, RV64E, Zc, and Zmmul specifications, each of which helps ensure that hardware implementations match the expectations of the RISC-V software ecosystem.
With these new additions to ImperasDV, Imperas hopes to enable RISC-V designers with the tools and flexibility necessary to reliably develop the next generation of RISC-V designs.
XMOS Rolls Out RISC-V SoC
Next up, XMOS released its new software-defined SoC platform for RISC-V. Specifically, XMOS announced that they’ll be employing a RISC-V compatible architecture for the fourth generation of its xcore platform.
Block diagram of the xcore.ai processor. Image used courtesy of XMOS. (Click image to enlarge)
One of the major reasons that XMOS has made the transition to a RISC-V-compatible architecture is that RISC-V is an open-source technology. Because of this XMOS hopes that the transition will provide embedded designers with more technical advantages, tools, and resources than could be achieved with a closed-source solution.
Additionally, XMOS states that the transition to a RISC-V architecture provides their designers with the flexibility to define entire systems in software. The result is that designers will be able to achieve faster time to market, greater design differentiation, and more economical solutions overall.
RISC-V Security Initiative Launched
Last but not least, at the RISC-V Summit this week Codasip announced the launch of a new RISC-V security initiative.
In some ways, security is more important in RISC-V than in other instruction set architectures (ISAs). A reason for this is that RISC-V is open-source, which means that anyone can access and modify the design. This openness has its benefits but also has shortcomings since security vulnerabilities can be more transparent and easily introduced if designs are not carefully managed.
Codasip CEO Ron Black presenting at the RISC-V Summit. Image from Codasip’s RISC-V Summit 2022 Spotlight session
To address this, Codasip’s new initiative, called SecuRISC5, is being launched with the goal of providing customers with a safe and secure custom compute platform based on Codasip IP as well as third-party technology. According to the news, the new initiative will build off of existing work from the RISC-V International Working Groups and will implement new standards as they are ratified.
For maximum visibility, and therefore maximum security, Codasip is partnering with a number of key industry players in this initiative. Specifically, groups like Intel and Crypto Quantique are supporters of the initiative.