Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development platform, and a system-level reference…
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development platform, and a system-level reference architecture to eliminate tail latency, maximize power efficiency, and scale agentic AI clusters.
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power…
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power alternatives to boost efficiency and lower BoM costs.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI…
The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI I/O, and robust security/reliability features for intelligent systems.
Announced today, the new AMD Versal Premium Gen 2 MoP SoCs boost performance by integrating memory on-package. It cuts…
Announced today, the new AMD Versal Premium Gen 2 MoP SoCs boost performance by integrating memory on-package. It cuts board space by 60% while gaining 288 GB/s bandwidth and 15-year lifecycle.
The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing…
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing fragmented funding, slow progress on FOAKs, and fierce international competition.
HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to…
HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to making FPGA development more accessible and productive for all engineers.
Altera Agilex™ 5 FPGAs and SoCs deliver a powerful balance of high performance, low power, and compact design for…
Altera Agilex™ 5 FPGAs and SoCs deliver a powerful balance of high performance, low power, and compact design for modern embedded and edge computing applications. Watch and learn all about their features, specs, applications, and more!
In this exclusive interview, the Seattle startup says its software-ML-hardware co-design—announced today—converts…
In this exclusive interview, the Seattle startup says its software-ML-hardware co-design—announced today—converts off-the-shelf FPGA servers into high-efficiency AI inference engines.
Announced today, the new FPGAs build off of AMD’s existing ecosystem with modernized memory, I/O, and security.
Announced today, the new FPGAs build off of AMD’s existing ecosystem with modernized memory, I/O, and security.
The new oHFM specification defines a common, scalable module framework for FPGA and SoC-FPGA designs, targeting…
The new oHFM specification defines a common, scalable module framework for FPGA and SoC-FPGA designs, targeting carrier-board reuse across vendors and deployment classes.
The latest members of the low-power, low-density FPGA product line feature instant-on with 896 to 9400 look-up tables.
The latest members of the low-power, low-density FPGA product line feature instant-on with 896 to 9400 look-up tables.
FPGAs are limited by outdated proprietary software. Learn how embracing open-source tools is necessary to modernize FPGA…
FPGAs are limited by outdated proprietary software. Learn how embracing open-source tools is necessary to modernize FPGA development and unlock their full potential.
The new low-power FPGAs include CNSA-2.0 compliance and hardware root of trust for post-quantum cryptographic security.
The new low-power FPGAs include CNSA-2.0 compliance and hardware root of trust for post-quantum cryptographic security.
Efinix has doubled its Titanium FPGA family, adding devices with transceivers up to 25.8 Gbps to support AI, edge, and…
Efinix has doubled its Titanium FPGA family, adding devices with transceivers up to 25.8 Gbps to support AI, edge, and industrial applications.
Today, the FPGA company revealed an array of new announcements at its annual Altera Innovators Day developer conference.
Today, the FPGA company revealed an array of new announcements at its annual Altera Innovators Day developer conference.
From fine-tuning the output of a solar farm to stabilizing a complex electric grid, FPGAs provide the ultra-fast,…
From fine-tuning the output of a solar farm to stabilizing a complex electric grid, FPGAs provide the ultra-fast, efficient computing needed to maximize energy efficiency.
The updated features of the low-power devices may give developers new ways to address the stringent thermal,…
The updated features of the low-power devices may give developers new ways to address the stringent thermal, connectivity, and size constraints of their designs.
In today's rapidly evolving aerospace and defense landscape, component engineers face an unprecedented challenge:…
In today's rapidly evolving aerospace and defense landscape, component engineers face an unprecedented challenge: ensuring every part they specify meets stringent compliance requirements while maintaining mission readiness and program viability.
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