SGeT Publishes oHFM, an Open, Vendor-Independent FPGA Module Standard

At CES 2026, the Standardization Group for Embedded Technologies (SGeT) published version 1.0 of the Open Harmonized FPGA Module (oHFM) specification, calling it the world’s first open, vendor-independent standard for FPGAs. The oHFM specification formalizes several years’ worth of work within SGeT’s HFM working group to address fragmentation in how FPGA system-on-modules are designed and integrated. 

SGeT claims that the new oHFM standard upholds a common signal language while acknowledging the different physical requirements of FPGA projects. 

FPGA modules are everywhere, from communications to embedded systems. Most, however, are designed around vendor-specific pinouts and power models, meaning that carrier boards are often tightly coupled to a single module family or silicon vendor. 

Even when two modules target similar devices, moving between them will usually require a carrier redesign. The oHFM specification may define a common module boundary that allows FPGA and SoC-FPGA modules from different vendors to share the same carrier infrastructure. 

Addressing Specialization and Lock-In 

FPGA vendors differentiate at the silicon level, and module vendors typically extend this to the board level, with power rails, I/O voltage groupings, and SerDes allocations frequently optimized for a specific device family. This can improve efficiency, but it also significantly limits interchangeability. The oHFM specification defines a harmonized interface separating what must be common and what can vary. 

The specification aims to remain chip-vendor agnostic and supports devices from vendors including AMD, Intel’s FPGA business, Lattice Semiconductor, and Microchip, among others. Instead of forcing identical pin usage across all models, the oHFM standardizes how power inputs, management interfaces, general-purpose I/O, and high-speed transceiver groups are presented to the carrier. The effect is that it allows a carrier board to be designed around capabilities rather than a specific FPGA. 

Powering this capability is a field-replaceable unit EEPROM, which stores identification data and supported I/O voltage information to allow a carrier to determine whether a particular module is compatible with its power and I/O configuration. Ultimately, this is a practical mechanism for managing variation without reverting to proprietary carrier designs. 

Two Variants, One Philosophy

oHFM is designed in two physical variants—oHFM.c and oHFM.s—which share the same philosophy.

The first, oHFM.c, is a connector-based module for high-performance designs and development use. It uses up to four high-density, board-to-board connectors and is designed to support large FPGAs and SoC-FPGAs with extensive I/O and transceiver requirements. According to the specification, there are eight form factors in this family, ranging from 75 mm x 50 mm up to 75 mm x 120 mm, with extended-length options for additional PCB area.

Diagram of oHFM.c, the connector-based variant. 

The smaller oHFM.c modules support high-speed lanes up to 64-Gbps PAM4 per lane, while the larger-sized variants are specified for up to 112-Gbps PAM4 per lane. Power is primarily delivered through a 12-V input, with a headline maximum current of 32 A along with management and backup rails. 

The second variant, oHFM.s, is a solderable module intended for cost-sensitive or space-constrained products. These modules are permanently attached to the carrier PCB and target applications that require features such as vibration and tamper resistance or simplified manufacturing. While oHFM.s modules expose fewer resources than oHFM.c, they follow the same interface rules, enabling designs to move between soldered and connector-based implementations with minimal architectural change. 

Depiction of oHFM.s, the solderable variant. 

Practicality for Carrier Reuse

The new specification also divides general-purpose I/O banks into defined categories with carrier-supplied voltages, while transceivers are grouped by predictable lane counts, thereby enabling carriers to anticipate how resources might grow as modules scale up.

It also addresses thermal considerations, with both of the new connector-based modules supporting more robust cooling, including heatsinks and cold plates. The solderable oHFM.s variant prioritizes low profile and direct thermal paths into the carrier.

In terms of licensing, SGeT has adopted a mixed model, with, for example, pinouts and integration guidelines published under a Creative Commons license. This allows developers to openly design carrier boards and reference implementations. Meanwhile, manufacturing design files and using the oHFM trademark are reserved for commercial licensing and SGeT membership. 

While the oHFM specification does not eliminate the inherent complexity of FPGA design or guarantee drop-in compatibility across all devices, it does offer a common starting point for designers by formalizing how FPGA modules scale and connect. With the new specification, SGeT is clearly attempting to shift FPGA system design to a more modular, predictable model.

All images used courtesy of SGeT.