Latest System-on-Chip Articles and Videos

Marvell’s OCTEON 10: The First DPU To Use Neoverse N2 ARMv9 Architecture

Marvell’s newest 5 nm data processing unit (DPU), the OCTEON 10, offers 3x improvement over the previous generation along with the newest ARMv9 Core.

July 07, 2021 by Adrian Gibbons

A RISC-V Future? SiFive and Andes Aim to Shake Up the Processor Industry

RISC-V, the open-source instruction set architecture, is making inroads against industry giants, with the support of the RISC-V Foundation.

June 25, 2021 by Adrian Gibbons

ARMv9: the Long-awaited High-Performance Computing Architecture

ARM Vision 2021 defines the company's roadmap for the next ten years of specialized computing with the ARMv9-A.

April 01, 2021 by Adrian Gibbons

STMICROELECTRONICS BlueNRG-LP BLUETOOTH® Low Energy Wireless SoC | New Product Brief

This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.

March 02, 2021 by Mouser Electronics

NORDIC SEMICONDUCTOR nRF52820 Bluetooth® 5.2 System-on-Chip (SoC) | New Product Brief

This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.

November 29, 2020 by Mouser Electronics

SiFive, Co-Founder of RISC-V, Unveils Major Upgrades to RISC-V-Based Processors

As the co-founders of RISC-V, SiFive's level-up on processors could have significant implications for custom SoC design.

July 25, 2020 by Vanessa Samuel

Revolutionizing Telecommunications Applications with Chip-Based Microcombs

Laser frequency combs small enough to fit on an IC have significant implications for frequency measurement and communications.

June 26, 2020 by Gary Elinoff

The International Telecommunication Union Announces a New Architecture That Incorporates MI Mechanisms

Recently, a study into the architecture has been presented by members of the Wireless Networking and AI&ML research groups and described as a “new standard” for telecommunications networks.

May 21, 2020 by Luke James

OpenHW Group Announces Multi-core Evaluation SoC Based on the NXP iMX Platform

The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.

December 13, 2019 by Cabe Atwell

Microchip Announces First RISC-V-based SoC FPGA to Use Half the Power of Other FPGAs

Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.

December 10, 2019 by Lisa Boneta

AI Hardware Built from a Software-first Perspective: Groq’s Flexible Silicon Architecture

Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that offers inference solutions for AI acceleration.

December 03, 2019 by Majeed Ahmad

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

September 10, 2019 by Ted Marena, Western Digital

Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

July 09, 2019 by Ted Marena, Western Digital

CHIPS Alliance Brings Powerful Players into Open Source Hardware Collaboration

Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?

July 08, 2019 by Gary Elinoff

The Advanced Microcontroller Bus Architecture: An Introduction

This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.

June 02, 2019 by Stephen St. Michael

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

May 14, 2019 by Zvonimir Bandić, Western Digital

Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

April 16, 2019 by Greg Sullivan, Dover Microsystems

The Arm Architecture Explained

Learn more about the Arm computer architecture, including ISA, execution states, and processor families.

April 10, 2019 by Stephen St. Michael

Running Hard Real-Time Applications and Linux on PolarFire SoC

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

March 26, 2019 by Tim Morin, Microchip

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

March 20, 2019 by Ted Marena, Western Digital

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