Lattice Outfits FPGA Portfolio With High I/O Density, Secure Options

Lattice Semiconductor has rolled out new additions to its Certus-NX and MachXO5-NX families, bringing more logic, higher I/O density, and enhanced security to compact, low-power FPGAs.

Built on the Nexus platform and backed by a full software stack, these devices target edge industrial, automotive, and compute applications where space is tight and reliability is non-negotiable.

More I/O, Less Overhead

Lattice’s latest Certus-NX and MachXO5-NX devices extend the company’s 28 nm FD-SOI Nexus platform, known for its extremely low power and compact form factors. The new Certus-NX devices scale to 65K logic cells, up to 380 programmable I/O, and 128 DSP blocks, while maintaining sub-watt power profiles and package footprints as small as 6 mm × 6 mm. That kind of I/O density makes them particularly suited for systems juggling multiple high-speed interfaces in space-constrained environments.

Example of the Certus-NX in a motor control application. 

The updates also bring support for 1.5 Gbps differential I/O, PCIe Gen1/Gen2, Gigabit Ethernet, and DDR3/LPDDR4 memory, features that aren’t always accessible in this power and size class. Built-in hardened functions further reduce the need for external ICs, especially in designs that need to boot fast and interact with multiple peripherals in real time.

Meanwhile, the new MachXO5-NX variants offer up to 96K logic cells, 355 I/O, and 55 Mb of ultra-fast flash memory. On-chip flash allows for fast boot (as little as 4 ms) and secure configuration updates, including encrypted bitstreams, ECDSA/RSA authentication, and support for zeroization, which is a key requirement in embedded control for automotive, industrial, and communications infrastructure.

Powered by Nexus and a Full Toolchain

Both families ride on the Lattice Nexus platform, built with 28 nm FD-SOI technology. Beyond power savings, this architecture brings significant reliability and performance benefits: 100x lower soft error rate (SER), 4x lower static power, and 12x faster boot times compared to traditional bulk-CMOS-based FPGAs. The FD-SOI process also enhances device immunity to radiation and transient faults—an essential feature for mission-critical and safety-focused designs.

The Lattice Nexus platform features a programmable back bias enabled by insulated gate of FD-SOI technology. This reduces size, improves SER reliability, and reduces processing steps. 
 

Toolchain integration is another cornerstone of the portfolio expansion. Lattice’s Radiant software supports the entire design flow, including synthesis, place-and-route, timing analysis, and bitstream generation. 

Recent updates have improved compile speeds by up to 25%, especially when working with large pin-count devices. Developers targeting control applications can also use Propel, Lattice’s SoC builder, which integrates RISC-V cores, AMBA buses, and memory maps through a visual interface. 

High Pin Count in Tight Spaces

Both families are designed for low-power, high-connectivity embedded systems, especially those that need a blend of performance, reliability, and secure control. Lattice points to use cases such as industrial edge systems, automotive subsystems, security and networking, communications, AI, and vision edge nodes. 

What sets the Certus-NX and MachXO5-NX families apart is their I/O-per-millimeter ratio, designed for pin-limited designs that previously had to scale up just to get enough I/O, even when the logic requirement was modest.

With this expansion, Lattice isn’t chasing the high-end SoC FPGA race. Instead, it’s reinforcing its position at the low-power edge of the market, adding security, I/O density, and scalability to designs where every milliwatt and square millimeter counts.

All images used courtesy of Lattice Semiconductor.