Bluespec Teams Up with Synopsys for RISC-V Core Verification Effort
With their collaboration, the firms hope to enable faster and improved functional verification testing for Bluespec’s RISC-V cores.
As the RISC-V movement gains significant traction in the industry, many engineers are finding exciting new ways of implementing the technology. Amongst these, RISC-V has become particularly popular with FPGA users, allowing for easy and open implementation of softcore processors.
One company that is working in this space is Bluespec, which designs RISC-V processor implementations specifically for Xilinx FPGA fabrics. Now, to bolster their efforts, Bluespec has teamed up with Synopsys to offer improved design verification tools for users of their technology.
Among Bluespec’s offerings are RISC-V soft cores for FPGAs and RISC-V cores specifically for Xilinx FPGAs. Image used courtesy of Bluespec
In this article, we’ll talk about the popularity of RISC-V in the world of FPGAs, and the collaboration between Bluespec and Synopsys.
RISC-V and FPGAs
As RISC-V becomes more popular, it is finding significant traction amongst FPGA enthusiasts, and for good reason. In many respects, the largest benefit of developing FPGA-based processors is the ease of development. Despite the need for programming in esoteric HDLs, FPGAs are a much simpler way of implementing custom hardware.
In contrast to FPGAs, standard chip development requires designers to go through the entire lifecycle associated with manufacturing a physical chip, an FPGA allows for processor development based entirely on software.
In the same way, RISC-V is a movement that is rooted in democratizing chip design. By providing an open-source, royalty-free instruction set architecture (ISA), RISC-V works to provide everybody and anybody with access to chip design.
With these commonalities, it is clear why FPGA enthusiasts have taken such a liking to RISC-V. At the intersection of FPGAs and RISC-V exists one of the most hassle-free straightforward ways of implementing processor cores. Ideally, this merger leads to greater design flexibility, simplicity, and decreased time to market for new products.
Bluespec and Synopsys Team Up
One company that is heavily involved in the development of RISC-V IP for FPGA implementations is Bluespec. Specifically, the company is known for its Xilinx-adapted RISC-V cores, which are a portfolio of RISC-V processors that were designed specifically for implementation in Xilinx FPGAs (Xilinx is now part of AMD).
Bluespec’s Universal RISC-V Controller (URC) block diagram. Image used courtesy of Bluespec
Last week, Bluespec announced a partnership with Synospsys to help facilitate the design and functional verification of Bluespec’s IP. Specifically, the partnership will work to provide reference methodologies for the verification and debugging of RISC-V system designs using Bluespec RISC-V cores. Within this, the partnership will center around the addition of Synopsys' EDA flows and methodologies to further support Bluespec’s specific IP.
The goal of the collaboration is to offer the RISC-V community proven methods to speed up the verification and debugging of RISC-V processors and systems. According to the companies, the first phase of the collaboration will offer reference methodologies and scripts for Synopsys' VCS functional verification solution and the Synopsys Verdi Debug System.
Synopsys claims that its VCS functional verification tool offers the highest performance simulation and constraint solver engines. Image used courtesy of Synopsys
Both of those Synopsys tools are Universal Verification Methodology (UVM) compliant. In addition, the companies will be working on methodologies for static, formal, portable stimulus, and FPGA synthesis.
With this collaboration, the companies hope to help engineers to improve their RISC-V designs and shorten time to market.