TSMC Teams Up With EDA Companies to Speed Up Design Flows

May 03, 2023 by Chantelle Dubois

With the rollout of new processing tech, TSMC is now teaming up with a number of prominent EDA and verification companies to accelerate design flows.

TSMC is partnering with several well-established EDA companies, including Synopsys, Cadence, Ansys, and Keysight Technologies, to accelerate the design flow process for chips in applications from automotive to hyper-scale computing. 


TSMC fab

Image (cropped) courtesy of TSMC


These collaborations are both tackling technical challenges across various applications while also giving TSMC an opportunity to advance the power, performance, and area (PPA) of its various process technologies from 3nm to 3DFabric.


N4AE and N3AE for Automotives

TSMC announced its intent to target the automotive industry at the 2023 North America Technology Symposium with the announcement of the N4AE and N3AE (4nm and 3nm auto-early, respectively) process nodes, which are variants of TSMC’s 4nm and 3nm process nodes.

The company hopes to address a unique cross-section of challenges for automakers: the higher standard of reliability and safety for automotive chips and the resulting lag in chip technology due to the extra development time to meet these standards. This means that chips used in vehicles can be several generations behind cutting-edge.


TSMC plans to extend its N3E to the automotive market

TSMC plans to extend its N3E to the automotive market. Image used courtesy of TSMC


Process design kits for both N3AE and N4AE are expected to be launched in 2023 and 2024, respectively, and can give vendors an opportunity to develop consumer-grade chip designs in anticipation of the N3A and N4A (3nm and 4nm automotive) process availability in 2025. TSMC is hoping this step-wise approach will allow early participants to turn around rugged chip designs two years faster than current processes.


RF and mmWave Designs for Autonomous Systems

Synopsys, Ansys, and Keysight Technologies are working with TSMC to create a new design process for advanced radio frequency (RF) and millimeter wave (mmWave) systems. This collaboration will result in a design reference flow for 79 GHz integrated circuits using TSMC’s 16nm FinFET compact technology (16FFC). 16FFC was first put into production by TSMC in 2016 and already has several years of proofing behind it.

This design process will benefit applications requiring high reliability, such as autonomous systems, 5G connectivity, and security systems, by reducing noise and improving the efficiency of power conversion.


TSMC’s 16nm FinFET

TSMC’s 16nm FinFET. Image used courtesy of TSMC


Synopsis is providing its custom compiler design environment; Ansys will be contributing its suite of multiphysics signoff analysis tools (VeloceRF, RaptorX, Exalto, and Totem); and Keysight will contribute electromagnetic analysis and circuit simulation using its Pathwave RFPro and RFIC Design tools.


2nm, 3nm, and 3DFabric

Meanwhile, Cadence and TSMC are partnering up on more than one front. Cadence has certified its digital and custom/analog flows using TSMC’s design rule manual for its N3E and N2 process nodes

This collaboration is meant to improve the design flow with a more efficient IC layout, such as grid-based structured device placement, improved analog migration, layout reuse functionality, and capabilities for integrated signoff-quality physical verification. In particular, this process can make migrating designs between TSMC process nodes quicker relative to manual migration. It will also benefit chip designers for mobile device, AI, and hyper-scale computing applications.

N3E is TSMC’s 3nm enhanced process node (second-generation 3nm), while N2 is its 2nm process node. N3E-based chips are planned to enter high-volume production in the second half of 2023, while N2-based chips are expected to enter production as soon as 2025.

Additionally, Cadence has introduced 3D-IC platform support for TSMC’s 3DFabric offerings such as Integrated Fan-Out (InFO), Chip-on-Wafer-on-Subststrate (CoWoS), and System-on-Integrate-Chips (TSMC-SoIC). This is intended to speed up the development of multi-die packages used in IoT, 5G, and mobile applications. 3D-IC provides system planning, packaging, and system-level analysis and uses the 3Dblox 1.5 specification.