Operation of a Linear Phase Detector for Clock and Data Recovery

Clock and data recovery (CDR) is vital for maintaining data integrity in asynchronous transmission, where the transmitter's clock is not sent separately. The receiver must reconstruct this clock directly from the data signal to ensure accurate sampling and synchronization. In this article, we'll examine a linear phase detector commonly used in CDR applications: the Hogge detector.

Understanding the CDR Challenge

Before we dive in, let's go over some relevant principles of clock recovery. Consider the non-return-to-zero (NRZ) data waveform in Figure 1.

Figure 1. An example input waveform that uses the NRZ data format.

In the NRZ format, the signal level stays constant throughout each bit period. As a result, the segment of the above waveform between t₁ and t₂, which maintains a high voltage level, is interpreted as a one. However, depending on the clock frequency used to generate the data, this segment can represent either a single one or multiple consecutive ones. Similarly, the portions that are at a low voltage level can represent one or multiple consecutive zeros.

While each flat segment can represent multiple bits, let's assume that the likelihood of encountering a zero is equal to that of a one. We would then expect the waveform to contain segments that alternate between representing a one and a zero.

In other words, the minimum duration of the constant-level segments in the waveform indicates the bit period (T_b). In Figure 1, the first such segment occurs between t₁ and t₂.

Before we can proceed further, we need to answer two questions. First, how can we extract a periodic clock from this random bit stream? And second, what would be the ideal frequency and phase for this clock?

Because we need to take a sample from the input data during every consecutive bit period, the clock period and the bit period should be equal. Furthermore, the sampling edge of the clock should coincide with the midpoint of the bits. This ensures that the sampling occurs at the point farthest from the data transitions, minimizing the effect of the data waveform jitter.

The bottom waveform in Figure 2 illustrates the ideal clock for our example, with the assumption that the rising edges of the clock serve as the sampling edges.

Figure 2. Input data waveform (top) and desired clock signal (bottom).

A sequence of consecutive ones or zeros in the data waveform is known as a 'run.' In the data waveform, there is a run of 3 bits from t₃ to t₄. The lack of transitions during this interval indicates that no frequency or phase information is present. How can the CDR circuit generate a periodic clock from the data waveform that lacks periodic transitions and doesn't provide phase or frequency information during its runs?

The CDR circuit needs to leverage the transitions in the data waveform to create a clock with a period of T_b and an appropriate phase alignment with the input data. During a run in which no frequency or phase information is available, the CDR circuit should maintain the previously acquired clock frequency and phase.

Note that long runs complicate CDR design. In practice, data is encoded to impose an upper limit on run length, as specified by the communication standard.

CDR Using PLLs

Phase locked loops (PLLs) are commonly used for recovering clock and data signals. In a PLL, the phase detector is responsible for detecting the phase difference between the input and the generated clock signal.

Considering the above discussion, it should come as no surprise that PLLs used in CDR applications need specialized phase detectors. For instance, an XOR phase detector is unsuitable for CDR applications because it continuously updates its output even in the absence of input data transitions.

Phase detectors for CDR must be capable of detecting input data transitions and adjusting their output according to the phase difference between their two inputs when a data transition occurs. This necessity arises from the fact that the input bit sequence is random and may remain unchanged for several consecutive bit periods. The rest of this article will focus on the Hogge detector, which is commonly used in CDR applications.

The Hogge Phase Detector

Shown in Figure 3 is the Hogge phase detector. You might remember this circuit from our discussion of the RS flip-flop phase detector. 

Figure 3. The Hogge phase detector.

In the Hogge detector, two distinct sections process the input data. The first section (FF₁ + XOR₁) samples the data stream on rising clock edges and XORs it with the delayed input to generate Up pulses. The second section (FF₂ + XOR₂) resamples FF₁'s output on falling edges and XORs it with FF₁'s output to create Down pulses. Together, the Up and Down paths provide the phase error information needed for clock recovery.

Role of the First Flip-Flop and XOR Gate

To comprehend the workings of the Hogge detector, let's begin by looking at the first section of the circuit in Figure 3 (FF₁ and XOR₁). The waveforms in Figure 4 will aid in this understanding.

Figure 4. Waveforms for the first section of the Hogge detector.

A D flip-flop captures the input value at the sampling edge of the clock and maintains it at the Q output until the next sampling edge. The Hogge detector leverages this data storage capability to compare the current data value with the previous sample held in the flip-flop to detect data transitions. In the waveforms presented here, we assume that the initial value stored in the flip-flop is a logic HIGH.

The flip-flop samples the input and updates the Q output at each rising edge of the clock. At time t = t₁, the input is logic-HIGH; at t = t₃, it's logic-LOW. Consequently, the output Q₁ remains HIGH at t = t₁ and transitions to a logic LOW at t = t₃.

The input data and the flip-flop output are applied to the XOR gate. The XOR compares the last sample with the current data value, generating a pulse that starts at the moment of the data transition and ends at the rising edge of the clock. Thus, the width of the pulse indicates the phase difference between the input data and the clock.

To illustrate this, compare the waveforms above with those displayed in Figure 5. In the new waveforms, the data transition takes place closer to t = t₁, resulting in wider pulses at the Up output.

Figure 5. These waveforms produce wider pulses at the Up output.

To summarize, the combination of FF₁ and XOR₁ detects transitions in the input data, generating a positive pulse at the output of the XOR gate for each data transition. The width of these pulses depends on the timing difference between the input data transition and the sampling edge of the clock.

Role of the Second Flip-Flop and XOR Gate

The Hogge detector's second section consists of FF₂ and XOR₂. From our earlier discussion, we understand that these two components work together to detect transitions at node A, creating a positive pulse at the XOR gate's output for each data transition. But what is the pulse width?

It's essential to recognize that transitions at node A occur at the rising edges of the clock due to the first flip-flop's operation (see Figures 4 and 5). However, the output of the second flip-flop (FF₂) changes at the falling edges of the clock. Consequently, transitions at node A always take place half a clock period before the sampling edge of FF₂. As illustrated in Figure 6, this means the pulses generated at the Down output have a fixed width equal to half the clock period.

Figure 6. Waveforms illustrating the operation of the second section of the Hogge detector.

The Final Phase Detector Output

The phase error can be determined by comparing the widths of the Up and Down pulses. To produce a signal that reflects the phase error, we subtract the Down pulse from the Up pulse and then integrate the result. In practice, the subtraction and integration functions can be achieved simply by applying Up and Down signals to a charge pump. Figure 7 shows the Up-Down signal and its integral for our example waveforms.

Figure 7. [click to enlarge] Waveforms illustrating the final output of the Hogge detector.

In this scenario, the Up pulses are narrower than the Down pulses. As a result, the average value of Up-Down is negative, leading to a decrease in the output of the loop integrator over time.

When the input data transitions coincide with the falling edges of the clock, the Up pulses will have a width equal to half the clock period. In this case, as illustrated in Figure 8, the Up-Down output has a zero average value and there is no net change in the loop integrator's output.

Figure 8. [click to enlarge] The Hogge detector's operation in the lock condition.

The above waveforms illustrate the circuit operation when the data and clock are optimally aligned, with the sampling edge of the clock occurring at the midpoints of the bits. While the integrator output exhibits fluctuations, its net value remains unchanged.

Note, also, that there are two fluctuations caused by the two transitions in the input data. The phase detector therefore tries to maintain its previous output during runs in the input data. This is a useful feature for CDR circuits.

Wrapping Up

This article explained how and why the Hogge phase detector is used in CDR applications. Despite its popularity, however, the Hogge detector does have some shortcomings. In the next article, we'll examine these problems and introduce a different phase detector that is designed to overcome them.

All images used courtesy of Steve Arar