LDRA Updates Tools to Automate Worst-Case Execution Time Analysis for RISC-V

Developers working on real-time and safety-critical systems—particularly in aerospace, automotive, medical, and industrial sectors—have long struggled with one persistent issue: predicting and verifying worst-case execution time in multicore environments. 

With its March 2025 update, LDRA has taken a direct step to remove this barrier for RISC-V users. The company’s tool suite now automates key analysis tasks that were once time-consuming and expensive, helping engineering teams build systems that are not only safe and secure but also deterministic and certifiable.

All About Circuits editor-in-chief Jeff Child (left) and LDRA’s VP of sales and marketing, Jim McElroy (right) at Embedded World 2025. 

“Fundamentally, the worst-case execution time analysis is utilized by our customers to guarantee deterministic behavior on the RISC-V architecture,” explained Jim McElroy, LDRA’s VP of sales and marketing at Embedded World 2025. “That’s really what this press release is about.”

Tackling Multicore Timing Challenges With Automation

Multicore processors boost performance by running code on multiple cores in parallel. But that comes at a cost. In many architectures, cores must share memory and cache, which introduces latency and unpredictability. One core accessing a shared cache can stall another core’s progress, and that interference can’t always be predicted or measured easily.

To manage these challenges, LDRA’s tool suite now performs automated analysis on how code interacts with shared resources—flagging access conflicts, identifying coherence risks, and measuring latency impact. These features work with RISC-V processors that include hardware-level multicore mitigation, such as Microchip’s low-latency memory allocation per core, which avoids shared cache altogether.

McElroy noted that these timing results can be captured directly from simulation environments or the physical target itself.

“We’re measuring the results of the worst-case execution times either on the host platform and simulation environment… or on the actual target hardware, which is where most of our customers do that analysis,” he said.

The LDRA tool suite automatically measures worst-case execution time to provide deterministic execution time for RISC-V processors. Image used courtesy of LDRA

These results can then be pushed into LDRA Vault, a web-based platform used to track timing trends across projects. This allows teams to review WCET data in context, spot regressions, and respond quickly to timing failures introduced by software changes.

Native Support for RISC-V Vendors and Toolchains

LDRA’s support covers multicore RISC-V implementations from Microchip, Synopsys, and Andes Technology and is tightly integrated with their ecosystems. For example, the tool suite now works with Microchip’s SoftConsole IDE, MPLAB X, and even MPLAB extensions for Visual Studio Code—providing developers with access to WCET and structural analysis tools within their existing workflows.

These integrations provide developers with tools for:

• Static and dynamic code analysis
• Structural and MC/DC coverage
• MISRA and security compliance
• Execution timing analysis on multicore hardware

By automating WCET analysis and aligning with existing IDEs and toolchains, LDRA reduces the friction of adopting RISC-V for safety-critical applications while still meeting demanding certification requirements.

Cutting Dev Costs and Risk in Safety-Critical Systems

Before this update, many companies relied on manual techniques or external consultants to estimate or measure WCET across multicore designs. This approach was expensive, error-prone, and slow, especially in systems where any code change could potentially invalidate earlier timing assumptions.

LDRA’s tool suite now brings this capability in-house. WCET analysis can be triggered automatically, integrated into CI pipelines, and repeated as often as needed—removing bottlenecks in safety verification cycles.

“We can feed these analysis results back into the web-based application LDRA Vault, so across the organization and across projects, users can look at the trends and make sure that they're addressing the time constraints on the particular software components of concern,” McElroy said.

The automation also helps teams meet timing deadlines required by industry standards without inflating project costs or timelines. For organizations working on systems that need to stay in operation for 10 to 20 years—such as aircraft, spacecraft, and energy infrastructure—this matters. Timing analysis must be repeatable and reliable across the lifecycle of a system, even as processors and compilers change.