SoC Evaluation Boards Evolve to Meet New Design Complexities

As SoC designs become more demanding, with more functions, higher pin counts, higher frequencies, and lower voltages, evaluation boards have become integral to the overall SoC project. High-performance boards are necessary to bring up and evaluate high-performance silicon. The board’s own limitations must not stand in the way of measuring the operating voltage range, operating frequency, and noise sensitivity, for example.

Increasingly, evaluation boards are used not only to characterize the silicon but also to perform system-level validation of the SoC and its application stack. So, the evaluation board must support all the functions and interfaces the system will use in the wild.

These requirements have pushed SoC evaluation boards far beyond just being a convenient way to hold a prototype SoC on an engineer’s bench. To do its job, the board must allow the SoC to operate in its intended environment, over its full range of operating conditions.

Its Own Project

Under these demands, the evaluation board has become a significant project in its own right. The board design must meet a range of requirements beyond simply housing the SoC and providing power and clocks. The layout may require specialists with high-frequency design experience and the appropriate tools. Further analysis for power integrity and signal integrity may be necessary.

Just as important, the supply chain for the evaluation boards becomes an issue. Not just any board fabrication shop or outsource assembly and test (OSAT) facility can successfully handle demanding boards like these. And among shops capable of handling them, it may be hard to find one willing to take a small-volume order on a tight schedule. Further, OSAT vendors are rarely equipped or trained to do the sort of system-level validation that SoC designers increasingly require.

For a well-funded SoC design effort within a large, integrated organization, these challenges may be purely internal. Such groups also tend to have strong relationships with specific outsource vendors, so something can be worked out to ensure a fast turnaround for a small lot of demanding boards. But for most SoC design efforts, these challenges represent significant additional effort and risk.

At Faraday, we have evolved a flexible, multi-phase engagement model to meet these needs for any customer, from a large organization that needs to outsource some prickly board design issues to a dedicated chip design team that will need help with every phase of the evaluation board effort. We present this range of engagement models as three discrete levels, although each level has great flexibility.

Three Kinds of Engagement

The most basic level of service is simply PCB design (Figure 1). The customer provides us with either a specification or a schematic for the evaluation board, and we provide a Gerber file of the completed board design. Our designers benefit not only from years of experience with SoC boards but also from a detailed understanding of Faraday’s and our vendors’ IP libraries.

We know from experience where the sensitivities are and what the performance will be for particular IP blocks on the chip. And because we are all in one house, our board design team can work directly with the die and package designers, co-designing the package and board for optimal performance and routing efficiency.

Figure 1. Shown here are the 3 levels of service. (Click on image to enlarge).

This level of service is best suited to SoCs that will not require detailed analysis of their board’s power, clock, and signal nets. Also, it assumes that the customer has existing relationships with internal or outsourced board fabrication and OSAT facilities.

But as SoCs have moved to higher speeds and lower operating voltages, it has become critical not just to follow best practices for board design, but to perform detailed analysis of power and signal nets. So our second level of service adds formal power-integrity and signal-integrity analyses to the design flow, iterates the design as needed to meet requirements, and provides SI/PI reports to the customer. We have delivered boards with 28 Gb/s signaling using this flow, and it supports signals up to 112 Gb/s.

For customers who would prefer not to be involved in creating a supply chain for high-performance evaluation boards, we offer a third level of service. At this level, we provide not only the design files and SI/PI reports, but also completed, tested evaluation boards. We contract with our own trusted PCB fabrication and assembly facilities, but we test in-house. In this way, we can maintain strict control of the testing process. But equally important, we can move beyond just silicon validation to place the SoC in a realistic system environment and perform system-level validation.

We can’t overemphasize the growing importance of this capability. Often, there are differences—often unanticipated—between the original design requirements for the SoC and the actual requirements the chip will face in the system. This may be good news: a parameter that limits die yield may not be critical in the actual software stack, in which case a change in chip testing could significantly improve yield. Or it may turn out that, for some reason, some chips that pass wafer sort will not function in-system, and chip tests will have to be altered. Either way, an intimate link between chip test, evaluation board design, and system-level test teams can be vital to improving system-level yield.

A High-Speed Example

Two examples can illustrate our engagement in real evaluation board projects. The first is an evaluation board for Faraday’s own HiSpeedKit. (Figure 2)

Figure 2. Faraday’s multi-purpose Hi-SpeedKit

The board is based on a Faraday-design SoC that includes a 1 GHz quad-core ARM Cortex-A53 CPU cluster, a PCIe Gen4 4-lane root port and endpoint, dual Gbit Ethernet ports, and a 3200 Mb/s DDR4 interface. In addition to allowing customers to evaluate a range of our high-speed interface IP, the board has been designed to function as a PCIe-to-Ethernet network interface card (NIC), a PCIe SSD device, or a memory-based storage subsystem controller.

The board design was challenging simply because of the speed and number of interfaces, and the need for them all to run concurrently. Here is where our knowledge of the silicon IP became vital. We knew that the PLL was particularly sensitive to power-supply noise. Similarly, the DDR4 PHY circuit was easily upset by simultaneous-switching noise on the supply pins. Both of these issues required detailed power-integrity simulations at the board level. Also, there was a SerDes highly sensitive to crosstalk, requiring signal-integrity analysis.

The SI/PI reports were extremely important to getting the evaluation board right. But equally valuable was our ability to bring up the SoC on the board and to prove correct system-level operation of the SoC with an application stack for each of the three application areas: NIC, SSD, and memory-based storage controller.

An IoT Example

A second example illustrates the importance of incorporating system-level test into the planning for an evaluation board. In this case, the SoC design was for an AI-enabled IoT application. The particular challenge was to design the evaluation board so it could be subjected to multi-board, parallel system-level testing using inexpensive automatic test equipment (ATE). (Figure 3.)

Figure 3. ulti-board system parallel testing on an inexpensive automatic test equipment

This required codevelopment of the board, its application software, the ATE test software, and an associated PC, and the interface between the test and PC environments and the evaluation board. For example, the dimensions of the evaluation board were dictated by the need to fit six boards at once into the test system for parallel testing to achieve the customer's desired test throughput. Further, we had to bring the customer’s application stack up on the evaluation board and control it from the test system. Once again, work between multiple teams became vital.

We believe both of these examples illustrate a growing trend in the development of evaluation boards for complex SoCs. Board designs are becoming far more demanding: of designers’ skills, of toolchains, and board supply chains. The growing importance of system-level testing on the evaluation board is adding new requirements not only for the board but also for the test facility.

We have found that the best response to these changes is a flexible engagement model that complements the customer’s existing strengths with our expertise and supply chain relationships. In that way, we can work together to meet these emerging challenges without our customers having to invest in hiring skilled engineers, adding new facilities, or establishing new outsource relationships that might not make business or strategic sense. It is a flexible, resilient way forward in an increasingly complex world.

All images used courtesy of Faraday Technology.