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Optimizing Power Management with NXP’s i.MX RT500 Crossover MCU

This article provides an introduction to microcontroller power management concepts. The NXP i.MX RT500 family of crossover MCUs will be used to provide examples of how these power management concepts can be employed by embedded developers in their applications.

July 08, 2021 by Alejandra Guzman, NXP Semiconductors

Understanding DSP Enablement Using NXP’s i.MX RT500 Crossover MCU

Learn about multi-threaded programs, developing applications using the XOS real-time operating system, resource sharing with semaphores, and how NXP's i.MX RT500 family of microcontrollers help engineers design DSP-enabled smart devices.

June 24, 2021 by Jason Tseng, NXP Semiconductors

Understanding the Heterogeneous Graphics Pipeline of i.MX RT1170 MCUs

In this article, learn about the heterogeneous graphics pipeline of the i.MX RT1170 MCU and its three main graphics acceleration engines.

March 18, 2021 by Hugo Osornio, NXP Semiconductors

Nine Factors to Consider for Board-Level Machine Vision Camera Integration

Leveraging board-level cameras offer a variety of benefits. To help identify the right mix of features and design elements, here are some factors to consider when selecting and designing in an embedded machine vision camera.

February 11, 2021 by Brian Cha, FLIR

Computing Fast Fourier Transforms on the LPC55S69 MCU

This article investigates the Transform Engine, another part of the PowerQuad, which enables the LPC55S69 MCU to compute a Fast Fourier Transform (FFT).

December 17, 2020 by Eli Hughes, NXP Semiconductors

Understanding Digital Filtering with Embedded Microcontrollers

Learn about the widely used methods for filtering and processing data samples in the time domain while taking a closer look at the Dual Biquad IIR engine of the PowerQuad unit in the LPC55S69 MCU. 

December 03, 2020 by Eli Hughes, NXP Semiconductors

Improving Home Appliance Safety with IEC Standards

This article explores the IEC 60730 Class B standard for functional safety to address both mechanical and electrical design in appliances. Learn what the standard entails and controllers to help meet these standards.

December 01, 2020 by Chad Solomon, Microchip Technology

How the PowerQuad Co-processor Frees Up CPU Cores in the LPC55S69 MCU

In this article, learn about the PowerQuad co-processor and its role in performing CPU-heavy tasks to allow the Arm Cortex-M33 cores to execute other tasks in the LPC55S69 MCU.

November 19, 2020 by Eli Hughes, NXP Semiconductors

Machine Learning and Intelligent Vision for the Industrial Edge

NXP’s i.MX 8M Plus applications processor enables machine learning and intelligent vision for consumer applications and the industrial edge. Learn about the features of this processor and how it can be used in embedded vision systems.

October 22, 2020 by Jeff Steinheider, NXP Semiconductors

An Example of Securing In-Cabin AI using TEE on a Secure FPGA SoC

This article discusses trusted execution environments — already used in a variety of connected devices — by showing how using TEE and an FPGA SoC can work in vehicle in-cabin AI.

July 28, 2020 by Katherine Hsu, Hex-Five Security

The Multi-Core and DSP Capabilities of the LPC5500 MCU Series

In this article, learn more about the multi-core, DSP acceleration, and co-processing features of the LPC5500 series of microcontrollers.

July 09, 2020 by Mark Dunnett, on Behalf of NXP

The Importance of Test Strategies for Multimedia Chipsets

Multimedia chipsets must exhibit a variety of characteristics to be considered for use in designs. Measuring their effectiveness requires a well-designed testing strategy.

June 29, 2020 by Chroma

How to Leverage the Arm TrustZone Security Features of the LPC5500

Learn how the Arm TrustZone extension for the LPC5500 series works and how to start utilizing the safety measures in custom secure and non-secure applications.

June 25, 2020 by Mark Dunnett, on Behalf of NXP

The Role of Last-Level Cache Implementation for SoC Developers

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.

May 12, 2020 by Kurt Shuler, Arteris

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

September 10, 2019 by Ted Marena, Western Digital

Meeting ASIL Compliance for ADAS with an Integrated SoC Power System Monitor

This article looks at the safety standard that governs ADAS features and the challenge in designing power monitoring systems to comply with this standard while introducing an automotive power monitor that has been certified to meet this standard.

September 06, 2019 by Michael Jackson, Maxim Integrated

Adding Custom Instructions to RISC-V to Boost Performance While Reducing Power and Code Density

The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.

June 20, 2019 by Tommy Lin, Andes Technology

Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

April 16, 2019 by Greg Sullivan, Dover Microsystems

Running Hard Real-Time Applications and Linux on PolarFire SoC

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

March 26, 2019 by Tim Morin, Microchip

CKB-VM as a RISC-V Instruction Set: Inspiration, Design, and Benefits

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

March 12, 2019 by Xuejie Xiao, Nervos