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How Mature-Technology ASICs Can Give You the Edge

How Mature-Technology ASICs Can Give You the Edge

Learn how application-specific integrated circuits can enable companies to leverage their key IP and distinguish themselves from competitors who use off-the-shelf ICs.


An AI Revolution in Power Management Design for Embedded Systems

An AI Revolution in Power Management Design for Embedded Systems

Learn how PMIC.AI leverages custom LLM technology to transform how engineers design power supplies that meet the increasing complexity of multi-rail SoC systems.


Last-Time Buy Notifications For Your ASICs? How To Make the Most of It

Last-Time Buy Notifications For Your ASICs? How To Make the Most of It

This article explores the history of the 600 nm process, the reasons behind its phase-out, and what the industry has to look forward to as smaller, more efficient chips become the new standard.


The 150-Year-Old Principle at the Root of Secure Silicon and Software

The 150-Year-Old Principle at the Root of Secure Silicon and Software

Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed correctly, managed well, and backed with appropriate resources.


Applying IP Customization to Improve AI Chips: A Case Study

Applying IP Customization to Improve AI Chips: A Case Study

For your next chip design, should you select a design-services provider with the ability to create custom fundamental IP blocks, including standard cells and libraries? This article will help you answer this question.


How Will Angstrom-Scale Chips Advance the Electronics Industry?

How Will Angstrom-Scale Chips Advance the Electronics Industry?

Angstrom-scale ICs will require innovation across the entire semiconductor ecosystem: This will include advances in both the hardware (transistors, power distribution, and connection of multi-die systems) and tools (EDA tools with AI/ML and silicon life-cycle management).


The Journey of RISC-V Implementation

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.


An Introduction to SweRV, a RISC-V Core

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.


How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.


Building Out the RISC-V Ecosystem

Building Out the RISC-V Ecosystem

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.