Industry Article

Building Out the RISC-V Ecosystem

December 20, 2018 by Markus Levy, NXP Semiconductors

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy and Robert Oshana of NXP weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.

It’s all about the ecosystem. It always was, and I’m guessing it always will be. The ecosystem topic du jour is RISC-V. Granted, it’s a new architecture—actually just an instruction set—but the ecosystem isn’t quite ready for prime time. It’s close, and getting closer every day, but it’s not yet where it needs to be for full-blown, mainstream product development and subsequently, for industry adoption.

For RISC-V to be successful in the long term, it requires a significant and deep ecosystem of partners and innovators that can push the RISC-V momentum forward. In particular, the software components must become more important.

What is and What is not an Ecosystem?

To be clear, let’s define what an ecosystem is. In my opinion, an ecosystem is a collection of interested parties focusing on driving architectural and software innovations. The various software components include middleware, security stacks, tools, and community support, all aligned, in this case, with moving RISC-V forward. It could (and should) also include open hardware—not just the cores, but all the “uncores” around it related to IP.

However, it’s important to understand what an ecosystem is not. It’s not a bunch of logos, as we’ve seen in numerous cases where quantity is more important than quality. The RISC-V tools must be as good or better than what we see supported for traditional architectures. The ecosystem is not big announcements with unrealized promises – the so-called partnerships that tend to fizzle once the marketing hype has passed.

Perhaps even more important, the success of RISC-V and its ecosystem should not be about people or companies using financial gain as the primary motivation. This is something we must warn against when we witness the openness of RISC-V being taken down a path of profit.

Finally, we must be careful to avoid fragmentation, it will eventually lead to stagnation as the ecosystem struggles to find stability. Although the RISC-V base instruction set is standardized, many are deriving various forks with specific implementations in mind. It’s critical that we look for common threads, avoid re-inventing the wheel, and standardize on application-specific functions – this will make it more feasible for tool vendors to provide support without customization.

Open Source is the Key

The RISC-V ecosystem is sure to get a boost from two recent announcements: the launch of Open-ISA.org and a new RISC-V-based development board named the VEGAboard.

 

the Vegaboard

Figure 1. The VEGAboard is designed to hasten the development of RISC-V based products. A secondary goal is to boost the RISC-V ecosystem.
 

 

The Open-ISA.org is a neutral group that can hasten the development of that ecosystem. The primary goal of this newly formed group is to support this open ISA community and foster ecosystem growth and expansion. It also serves as a place where developers can share ideas and experiences and act as a discussion board for topics related to RISC-V. Its founders pledge that it will remain open to any and all relevant ecosystem partners. The organization’s website is for open-source ISA enthusiasts (think Raspberry Pi).

The VEGAboard

The VEGAboard is a contribution to the RISC-V community/ecosystem and will be used to help kick-start and advance the ecosystem to the benefit of the entire RISC-V community. To become part of the Open-ISA.org community, you simply need to sign up—no fees are required. Once there, you can order the VEGAboard (aka RV32M1-VEGA) either for free or at a significantly subsidized price and download all the associated documentation, software tools, middleware, and utilize various ‘getting started’ videos. Open-ISA.org has a “Git feel” to it so developers should not have any trouble navigating. It’s designed for individuals, Makers, and MakerPros.

The VEGAboard is designed to significantly cut the development time for RISC-V-based designs. It’s a small, low-power and cost-effective evaluation and development board for application prototyping and demonstration of a RISC-V-based microprocessor (more about that later). Key features of the RV32M1-VEGA development board include Bluetooth Low Energy (BLE), an integrated PCB antenna, 4 Mbytes of flash memory and 384 Kbytes of SRAM.

 

VEGAboard block diagram

Figure 2. The block diagram shows the various functions of the VEGAboard.

 

But what really makes this development board unique is its MCU – besides being a fully-integrated SoC, it contains a quad core CPU – sporting a combination of an ARM Cortex-M4 CPU, an ARM Cortex-M0+ CPU, a RISC-V RI5CY CPU, and a RISC-V ZERO_RISCY CPU (both RISC-V cores originate from PULP open cores). Yes, you read that right. You can develop an application that takes advantage of just the RISC-V core or you can utilize the features of both the ARM and RISC-V cores simultaneously. This is where you’ll likely be diving into the features of the Open-ISA.org site, looking for code and other support. On the prototype processor, the two RISC-V cores are running the Zephyr open-source operating system as well as Free RTOS.

The RISC-V Ecosystem Today

While there’s already the basis for a workable ecosystem, it’s not where it needs to be for full-scale success. The early adopters in the ecosystem include Ashling Microsystems, who are building tools to support the board. The company offers RISC-V products based on its Ashling RiscFree platform. Those products include simulation, debug, probes and development tools.

Engineers at the Swiss University ETH Zurich have contributed the 32-bit PULPino core, an open-source microprocessor based on the RISC-V instruction-set architecture. Going forward, the university will use the VEGAboard as part of its engineering curriculum.

Express Logic has been in the RISC-V game for quite some time, and now it’ll support Open-ISA and the VEGAboard. The company’s ThreadX real-time operating system combines with its X-Ware IoT platform to form a comprehensive deeply embedded run-time offering for RISC-V.

IAR Systems, well-known for its Embedded Workbench development tool and one of the bellwethers of the embedded industry, has pledged support for RISC-V and the VEGAboard and will be part of Open-ISA.org.

Segger, an early member of the RISC-V Foundation, has ported its tools to support RISC-V, particularly its debugging tools aimed at integrated software development. The SEGGER Software Platform, including development tools, debug probes and middleware, provides a comprehensive RISC-V product development solution. And now, support for the VEGAboard is now part of the company’s arsenal.

Foundries.io recently joined RISC-V. The company has ported its Zephyr microPlatform to the VEGAboard and has demonstrated some levels of connectivity with it. The microPlatform combines the MCUboot secure bootloader, the Zephyr RTOS, and reference firmware applications to provide an over-the-air updatable, cross-architecture solution for RISC-V-based products, including the VEGAboard and adds a higher level of connectivity. One point previously not mentioned is that the board also integrates a radio transceiver operating in the 2.36- to 2.48-GHz range, which Foundries.io has utilized to implement two flavors of LTE communication.

The bottom line is that the building of the RISC-V ecosystem has commenced. Now we need to take it to the next level. Join the Open-ISA.org and add to the community and/or the growing partner program that will help drive the success of RISC-V.

 

This article was co-authored by Robert Oshana, Vice President of Software and R&D at NXP.

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