SiFive, the originator of the first open-source chip platform, is amassing tools and cores necessary to build custom chips based on the free and open RISC-V instruction set architecture (ISA). A number of companies are making their IPs available through SiFive's DesignShare model that is aimed at significantly reducing the upfront engineering costs needed to develop a custom chip.
The goal—as SiFive's new CEO Naveed Sherwani puts it—is to create a level playing field for anyone who wants to develop a custom chip. Here is how SiFive is streamlining the development of custom silicon by signing up one partnership at a time.
Rambus Offering Security Cores
As part of SiFive's DesignShare model, which facilitates a catalog of IPs at lower costs, Rambus will make available cryptographic cores, hardware root-of-trust, key provisioning, and other security-related components.
That will allow chip developers to easily embed security cores into SiFive's Freedom platforms for developing custom system-on-chips (SoCs). And it's going to be a critical feature for securing the Internet of Things (IoT) end-points and in-field device connections.
eMemory's IP for Logic NVM
SiFive has also added to its catalog of low-cost IPs the logic-based non-volatile memory (Logic NVM) technology from eMemory Technology Inc. It's an embedded memory solution that eMemory licenses to semiconductor foundries, IDMs, and fabless design houses.
Silicon IPs for OTP, MTP and EEPROM memory blocks. Image courtesy of eMemory Technology Inc.
The company claims that its embedded memory IP has been employed in more than 27 billion chips used in applications like consumer, industrial, and automotive. Its proprietary silicon IP technologies include NeoBit, NeoFuse, NeoMTP, NeoFlash, and NeoEE.
UltraSoC's Embedded Analytics IP
SiFive's Freedom design platform, which is based on open source RISC-V processor cores, is also amassing a variety of tools and interfaces. Take, for instance, UltraSoC, the supplier of vendor-neutral on-chip debug and analytics tools. UltraSoC is making available its embedded analytics IP for SiFive's DesignShare initiative.
Chip designers can use this debug and trace technology to gain an intimate understanding of the interactions between on-chip processor blocks, custom logic, and system software. Trace is a basic requirement for developers working on any processor architecture; it allows them to view the behavior of their programs in detail and subsequently isolate bugs and identify areas for improvement.
Debugging Toolset from Lauterback
Lauterbach, a supplier of microprocessor development tools, has also announced support for SiFive's RISC-V cores. Lauterbach’s TRACE32 toolset will provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, which is based on the free and open RISC-V instruction set.
The TRACE32 toolset is planning support for debug interfaces like USB. Image courtesy of Lauterbach GmbH.
The toolset provides multicore debugging on individual hardware threads of SiFive cores, right from the reset vector to analyzing startup codes and other key functions.
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