This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

Advancements in machine learning, analytics and other data-centric applications are increasingly leading to new capabilities and insights for autonomous vehicles, customized medicine, preventative maintenance and more. Yet their potential is limited by traditional one-size-fits-all processors and technologies. To fully unlock their potential will require us to move beyond the general-purpose processors, to purpose-built processors, such as RISC-V provides.

This reality is driving increasing popularity behind RISC-V (Reduced Instruction Set Computing – 5th iteration). RISC-V is unleashing a new level of innovation by leveraging the power of an open standard for a broad range of purpose-built processor requirements. Similar to the growth that Linux® has generated for software, RISC-V has the potential to disrupt hardware. What is most noteworthy is that organizations and individuals are interested in RISC-V for a variety of different reasons. Whether you are a software manager, system architect, design engineer, or a CTO, the benefits of RISC-V are compelling. Technology companies of all kinds see different benefits to embracing RISC-V.  


Why Use RISC-V?

To understand the reasons why RISC-V adoption is growing, we need to explain the basic specifications behind the standard. To begin with, RISC-V is an open instruction set architecture (ISA), not a processor architecture. RISC-V is a true reduced instruction set. The required base instructions total less than 50. All the approved optional extensions total to less than 150. Other popular RISC architectures have more than a thousand instructions by comparison. Figure 1 has the complete RISC-V ISA.


The complete RISC-V ISA

Figure 1. The complete RISC-V ISA.


Not only is the total number of instructions far fewer, but the ISA is actually frozen. The base instructions and all the approved extensions are frozen forever. Other popular processor architectures often add instructions as each new generation of devices is produced. Although the RISC-V ISA is frozen, instructions can be added by approved extensions. Through the technical task groups in the RISC-V Foundation, extensions can be approved and when ratified will be frozen as well. This provides a secure base to develop upon but also provides flexibility via future extensions. With a stable ISA, software written for RISC-V will run on a similarly configured core forever.

The RISC-V ISA is completely open for all to use. By exposing all the instructions, various types of core implementations are possible. RISC-V also allows for an option to implement custom instructions. This enables far more customization than is available from off-the-shelf processor alternatives. The RISC-V platform allows the creation of purpose-built solutions that can deliver the value from data-centric applications. For example, a RISC-V SoC with custom instructions to implement vector multiplication could improve the performance of a machine-learning neural network.

Now that the attributes of RISC-V have been explained, let’s look at how individuals and organizations can benefit from this innovation.


Board Designers: Portability and Security

In addition to the frozen ISA benefits, RISC-V’s open ISA also provides portability for hardware engineers. For example, if designers are implementing a soft RISC-V core in a FPGA (Field Programmable Gate Array), often the RTL source code is available. The Western Digital SweRV Core™ seen in figure 2 is an example of an open sourced core. Since RISC-V is royalty free, this creates significant flexibility to port a RISC-V based design from a FPGA to an ASIC or another FPGA. No software modifications are required when porting the code. For designs which must be supported for long periods of time, the portability of RISC-V is of significant value.


Figure 2. The SweRV Core Block Diagram

Figure 2. The SweRV Core Block Diagram


Applications which demand high security can also benefit from RISC-V. Because the ISA is open, many organizations are sharing their RISC-V core RTL source. Because of this, trust can be established.  When the RTL source code is shared and available to view, it enables deeper inspection and evaluation of its applicability for a broad range of applications.


Software Architects and Designers: Stability and Hardware Influence

As previously stated, RISC-V is much more than an open ISA, it is also a frozen ISA. Because of the stability of the ISA, software development can confidently be applied to RISC-V knowing that your investment will be preserved. Software written for RISC-V will run on all similar RISC-V cores forever. The software life cycle is significantly extended given the stability of the ISA.

Because the RISC-V ISA is open, hardware engineers have more flexibility over the processor implementation. Knowing this, software architects can become more influential in the final hardware implementation. One method to do this is by leveraging the program language Chisel. Although Chisel is a higher level hardware language, software designers can use it to model their code and see the most commonly used instructions. This allows specific inputs to hardware engineers so they can optimize a RISC-V core. In summary, software engineers can now have significant influence over hardware designs to make the RISC-V processor more software-centric.


CTOs, Chip Designers, and System Architects: Configurability and Open Standard Interfaces

Because the RISC-V ISA is open, it is the equivalent of everyone having a micro-architecture license. One can optimize designs for lower power, performance, security, or other key parameters while keeping full compatibility with other designs. Because there is significantly more control over the hardware implementation, the SoC can be exactly what is required for a data centric application. 

RISC-V enables one to choose the interfaces, buses, and peripherals that are best for the solution. A recent example is Western Digital’s OmniXtend™, a cache coherent fabric, based on an open standard bus for tightly coupled, low latency RISC-V SoCs. Serializing this bus and placing it over Ethernet creates a cache coherent fabric as seen in Figure 3.


Figure 3. OmniXtend open standard interface for cache coherent fabric

Figure 3. OmniXtend open standard interface for cache coherent fabric.


The flexibility of RISC-V enables purpose-built architectures such as this to be a reality. Innovations with RISC-V may solve the challenges of maximizing the value of data. RISC-V provides us a new path to create data centric solutions for current and future workloads.   


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