This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.
July 09, 2019 by Ted Marena, Western Digital
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.
May 14, 2019 by Zvonimir Bandić, Western Digital
Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.
March 12, 2019 by Xuejie Xiao, Nervos
The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.
March 05, 2019 by Xuejie Xiao, Nervos
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