Rambus Serves Up DDR5 RDIMM Server Chipset for Next-Gen AI Data Centers

Memory has been at the center of industry conversation in recent months, and that trend doesn’t seem to be slowing down any time soon. Recently, Rambus announced its DDR5 9600 Server RDIMM chipset, a complete set of interface and power-management ICs for registered dual in-line memory modules (RDIMMs).

Rambus DDR5 9600 Server RDIMM chipset. Image used courtesy of Rambus

AI data centers need more memory at faster speeds to support large-scale inference and agentic workflows. Rambus believes its new products could be a true difference-maker for server architectures. 

Rambus DDR5 9600 Server RDIMM Chipset

Rambus built the DDR5 9600 Server RDIMM chipset to give memory module manufacturers greater memory capacity and bandwidth to support growing AI workloads.

At the center of the chipset is a new sixth-generation Registering Clock Driver, the RCD06, which runs at 9,600 MT/s. Because it offers 20% higher frequency than the company's previous driver, the RCD06 should offer meaningful performance improvements for AI’s memory-hungry workloads. For example, one common AI workload, key-value (KV) caching, stores context in DRAM and reads it back constantly to speed up token generation. The faster each memory channel runs, the more traffic it can carry, and the faster it can complete inference.

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High-level functional block diagram of the DDR5 RCD06. Image used courtesy of Rambus

Rambus’ RCD06 clock driver is only one part of the server memory chipset. The company also includes the PMIC5030 power management IC, which feeds the module high-current power at low voltage, and a Serial Presence Detect (SPD) Hub, which carries a built-in temperature sensor onboard. With a set of dedicated temperature sensor ICs, these components are said to enable module telemetry, configuration, and thermal monitoring.

By putting clocking, control, and power management on one set of qualified parts, Rambus says its memory chipset gives memory manufacturers a cohesive and interoperable path to maintaining signal and power integrity at high data rates. The company also claims that the chipset’s integration spares vendors from sourcing and testing extra components on their own, reducing their need for external components and simplifying RDIMM development.

Server Memory and the Command Bus

In a server, one memory channel must feed many DRAM chips at once, often organized into several ranks on a single module. That large number of chips is a problem for ordinary unbuffered memory, where the memory controller drives every chip directly. Each chip adds electrical load to the shared command and address bus, and once enough of them use that bus, the signals degrade, and the bus can no longer run quickly or reliably.

Registered DIMMs solve this problem by placing a register, a small buffer, between the controller and the DRAM chips. The controller only drives the register instead of dozens of chips, and the register re-drives the command, address, and control signals the rest of the way. Because the controller only manages a single load, a server module can hold far more memory without overwhelming the bus.

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Comparison of registered DIMM (RDIMM) and load-reduced (LR-DIMM). Image used courtesy of Exxact

The memory register matters even more as data rates grow. At higher speeds, each command is valid for less time, and at 9,600 MT/s, that window is only picoseconds wide. The register re-times and re-sends every signal so it still arrives inside that window, allowing the module to maintain its rated speed.

Potential Implications for AI Servers

Server memory manufacturers want to produce high-bandwidth, high-capacity memory for agentic AI and other data-intensive workloads, without adding cost or development complexity. With the DDR5 9600 Server RDIMM chipset, Rambus hopes it can help such vendors build higher-performance, scalable memory subsystems that can keep pace with next-generation AI and cloud infrastructure.​