IMEC and Diraq Tow the Quantum Line With Foundry-Compatible Spin Qubits

Interuniversity Microelectronics Centre (IMEC), a Leuven, Belgium-based research hub, and Diraq, a Sydney, Australia-based silicon quantum computing company, recently announced the coherent operation of an eight-silicon-MOS spin-qubit array. IMEC fabricated the array on its 300-mm, CMOS-compatible process.

The IMEC/Diraq eight-silicon-MOS spin-qubit array. Image used courtesy of IMEC,

While an eight-qubit array may not sound significant compared to other organizations announcing quantum processing units (QPUs) exceeding 1,000 qubits, the standard CMOS fabrication process in this announcement holds significance for scalability.

Fabrication and Coherence Challenges

Two of the greatest challenges facing the quantum computer industry are scalable QPU fabrication and qubit coherence.

Coherence—the ability to maintain a quantum state over time—is the primary limiting factor with quantum computers today. A qubit must maintain superposition or entanglement, or it loses its ability to hold data and perform calculations. Poor coherence in a qubit is much like an unstable conventional bit or latch that randomly changes value. 

Fabrication presents another major challenge for scaling to commercially viable qubit densities. Most qubits require materials and manufacturing techniques that are currently not compatible with semiconductor mass production. They may require exotic chemistry, challenging optomechanical materials, and submicron alignment of waveguides and lasers.

In 2025, researchers from IMEC and Diraq demonstrated viable coherence levels with a two-qubit-MOS spin-qubit array fabricated on standard or near-standard 300-mm CMOS processing equipment. The latest eight-qubit array announcement shows scaling ability while maintaining qubit coherence. 

Silicon MOS Spin-Qubits

IMEC and Diraq created their spin qubits with silicon metal-oxide-semiconductor (SiMOS) quantum dots. Quantum dots are nanoscale semiconductor crystals that can manipulate a single electron. Prior quantum dot qubit arrays have been fabricated with materials such as germanium (Ge) and silicon/germanium (Si/Ge), which are not compatible with standard fab processing.

While SiMOS quantum dots are easier to manufacture, until this research, they have been limited to two-qubit arrays. The new research yielded the first successful CMOS array larger than two qubits.

Diagram illustrating the operation and calibration of an eight-dot device. Image used courtesy of Nature

A CMOS quantum dot starts with a silicon substrate covered with an insulating oxide layer a few atoms thick. Metal gate electrodes top it off. The gates create a field, allowing the system to tune voltages until a single electron is under control in the dot. The electron becomes the qubit. A titanium-nitrogen (TiN) stripline microwave antenna, located above the gate electrodes, creates an oscillating magnetic field to control the qubits.

Test Setup Architecture

The test setup configures the outer two qubits on both sides as two-qubit gates. The team used the inner four qubits as a cascaded charge sensing architecture. In future iterations, the researchers plan to downscale from the 90-nm geometry and pitch used here. Future development efforts will also place the qubits closer together, enabling larger arrays.

By leveraging industry-standard, 300-mm CMOS processing, the researchers access a well-worn path for scalability and bypass the more exotic process technologies in common QPU use today.

Closeup showing the simplified connection architecture of the eight-silicon-MOS spin-qubit array. Image used courtesy of IMEC

The CMOS spin qubits demonstrate the coherence necessary to create quantum gates and perform quantum math. The researchers report that their quantum dot spin qubits produce low and consistent charge noise across devices with single- and two-qubit gates, with fidelities exceeding 99%.

IMEC and Diraq expect to scale this new architecture faster than competing QPU architectures. The ability to utilize conventional infrastructure, supply chains, and manufacturing expertise promises to remove process and scaling hurdles.