Latest Logic Synthesis Articles and Videos

Summary

Summary

This article explores using PSpice for TI to simulate potential causes for parasitic effects in a motor-drive design and…

This article explores using PSpice for TI to simulate potential causes for parasitic effects in a motor-drive design and offers design tips to mitigate the negative effects common with high-power motor-drive systems.

This article shows a comparison of the implementations that result from using binary, Gray, and one-hot encodings to…

This article shows a comparison of the implementations that result from using binary, Gray, and one-hot encodings to implement state machines in an FPGA. These encodings are often evaluated and applied by the synthesis and implementation tools, so it’s important to know why the software makes these decisions.

This article discusses the use of finite state machines (or FSMs) in design, including the initial state and the way…

This article discusses the use of finite state machines (or FSMs) in design, including the initial state and the way memory configuration affects FPGA design.

This article describes the basics of finite state machines and shows a practical way of implementing them in the Verilog…

This article describes the basics of finite state machines and shows a practical way of implementing them in the Verilog Hardware Description Language.

Learn the high-level overview of digital integrated circuit (IC) design.

Learn the high-level overview of digital integrated circuit (IC) design.

Analysts predict that DDR5 will dominate the DRAM market in coming years. How do you calibrate DDR for peak memory performance?

Analysts predict that DDR5 will dominate the DRAM market in coming years. How do you calibrate DDR for peak memory performance?

Social distancing doesn't mean your productivity must come to a halt.

Social distancing doesn't mean your productivity must come to a halt.

This F_EQ (or Frequent Engineering Question) covers the basics of a crucial topic: hardware description languages.

This F_EQ (or Frequent Engineering Question) covers the basics of a crucial topic: hardware description languages.

Learn how simulating a voltage buffer can help you implement it more effectively to boost the output current drive of an op-amp.

Learn how simulating a voltage buffer can help you implement it more effectively to boost the output current drive of an op-amp.

In this entry of our Frequent Engineering Questions (F_EQ) series, learn the basics of how a load line can be used in…

In this entry of our Frequent Engineering Questions (F_EQ) series, learn the basics of how a load line can be used in designing circuits.

In this article, we’ll perform some classification experiments and gather data on the relationship between hidden-layer…

In this article, we’ll perform some classification experiments and gather data on the relationship between hidden-layer dimensionality and network performance.

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability…

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability verification of AI/ML processors is critical since failures can have major consequences for the validity and legitimacy of AI/ML technology.

The P348 is designed for transducer simulation and provides carrier frequencies over a range of 0.5MHz to 20MHz.

The P348 is designed for transducer simulation and provides carrier frequencies over a range of 0.5MHz to 20MHz.

This article describes a methodology that automates set up, constraints, and results analysis as designs move from static…

This article describes a methodology that automates set up, constraints, and results analysis as designs move from static CDC analysis to formal verification to simulation and avoid manual scripting efforts, thus reducing setup effort and errors.

Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso…

Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso Periodic Steady State (PSS) analysis.

This article introduces and explores advanced ERC, highlighting its differences from traditional ERC and discussing how…

This article introduces and explores advanced ERC, highlighting its differences from traditional ERC and discussing how it can help create better circuit designs.

This article looks at the common options for a four-layer board stackup.

This article looks at the common options for a four-layer board stackup.

This article will discuss how to implement a shift register in Verilog. The register described can be synthesized and…

This article will discuss how to implement a shift register in Verilog. The register described can be synthesized and downloaded to an FPGA for test in actual hardware.