Technical Article

What Is Digital IC Design?

December 02, 2020 by Jean-Jacques DeLisle

Learn the high-level overview of digital integrated circuit (IC) design.

In this article, we'll discuss the process of digital IC design and break it down into steps. 

 

What Is Digital IC Design?

Digital IC design is a procedural process that involves converting specifications and features into digital blocks and then further into logic circuits. Many of the constraints associated with digital IC design come from the foundry process and technological limitations.

Design skill and ingenuity are key at the higher level stages of digital IC design and the development of systems and processes that ensure a design meets specification as efficiently as possible.

 

Image used courtesy of Takuya Abe. [CC BY-NC 2.0]

 

Synthesis and Verification: Hardware Description Language and Functional Verification

The digital blocks with behavior descriptions developed in the early phases of digital design need to be translated into a hardware description language (HDL), such as Verilog or VHDL. This phase is often called the Register Transfer Level (RTL) phase, which generally includes functional verification to ensure that the logic implementation meets specification at a high-level.

 

(a) An example of HDL code and (b) the circuit it describes

 

After this step, the hardware description is then converted into a gate-level netlist, during which a variety of implementations and optimization routines may be tried to better meet design goals. Important considerations at this stage include power budget, speed, footprint, and reliability.

 

Physical IC Layout: Floorplanning and IP Cores

After synthesis and verification, the gate-level netlist is transformed into physical layout, which is a geometric representation of the layers and physical structure of the IC. Floorplanning methods are employed to ensure placement of the blocks and pads throughout the IC meet design goals.

Due to the structured and repetitive nature of some digital blocks, such as memory and registers, portions of digital IC layout are often done using scripts and automated software processes. External IP cores are also placed during this stage, where only the necessary interface portions of the IP are revealed by the software. After all blocks and gates are placed—along with manual routing, if necessary—routing automation scripts and software are used to connect every element. 

 

Verification and Simulation: Tapeout and Testing

Verification and simulation is then performed, both of which must take into account the placement and the physical features of the layout. If successful, the result is an output file, such as GDSII (GDS2), which the foundry uses with internal software and processes to fabricate the ICs, the tape-out stage. In some cases, the foundry discovers issues with the design that then needs to be corrected/confirmed by the design team.

 

The layout of a chip after place and route. Image used courtesy of Cadence Design Systems.
 

After tape-out, a small batch of first-run or prototype ICs are produced so that testing can be performed. This testing may result in redesign or process changes depending on the performance and economics of producing the IC.

 

Digital Integrated Circuits Abstraction Levels

  1. Behavioral
  2. Register Transfer Level (RTL)
  3. Functional
  4. Gate
  5. Transistor
  6. Physical layout

 

Digital IC Design Flow

  • The following list outlines the steps in the digital IC design flow, including substeps:
  • Design Specification
    • Specifications
    • Constraints
    • Test bench development
  • High-level system design
    • Design Partition
    • Entry-Verilog Behavior Modeling
    • Simulation/Functional Verification
    • Integration & Verification
  • Logic Synthesis
    • Register Transfer Level (RTL) conversion into netlist
    • Design partitioning into physical blocks
    • Timing margin and timing constraints
    • RTL and gate level netlist verification
    • Static timing analysis
  • Floorplanning
    • Hierarchical IC blocks placement
    • Power and clock planning
  • Synthesis
    • Timing constraints and optimization
    • Static timing analysis
    • Update placement
    • Update power and clock planning
  • Block Level Layout
    • Complete placement and routing of blocks
  • IC Level Layout
    • IC integration of all blocks
    • Cell placement
    • Scan chain/clock tree insertion
    • Cell routing
    • Physical and electrical design rules check (DRC)
    • Layout versus schematic (LVS)
    • Parasitic Extraction
    • Post-layout timing verification
    • GDSII creation
    • Tape-out

In the next part of this series, we'll discuss analog IC design and RFIC design.