The World’s First 3nm Tapeout: Cadence and Imec Demonstrate Novel Lithography Techniques
Cadence Design Systems and Imec have recently introduced the world’s first 3nm tapeout. The companies have achieved a reduction in size of transistor (FinFET) nodes which will allow even more transistors to be packed onto a chip.
News Brief: Cadence Design Systems and Imec have announced the world's first 3nm tapeout, allowing smaller transistor (FinFET) nodes and opening the door to more transistors on a single chip.
Cadence Design Systems and Imec's 3nm tapeout can allow even more transistors to be packed onto a chip. This is an expansion of work between the two companies which last produced a 5nm tapeout in 2015.
The companies achieved this using extreme ultraviolet and 193 immersion lithography techniques along with Cadence’s Innovus Implementation System and Genus Synthesis Solution. A test chip of a 64-bit MCU was produced, using a 3nm standard cell library, TRIM metal flow, and a routing pitch of 21nm.
Cadence and Imec made the announcement at the 2018 SPIE Advance Lithography Conference, where semiconductor companies, experts, and researchers come together to exchange ideas knowand news on the latest manufacturing and materials problems.
Layout of chip after place and route with 21 nm pitch metal layers. Image courtesy of Cadence Design Systems.
This is a big step in nano-electronics as silicon designs begin to reach their limits in terms of size. Making smaller transistors is a major challenge, especially from a manufacturing standpoint as precision and accuracy are critical at nano-sizes.
Moore’s Law, which stipulates that a silicon chip should double in transistor density every two years, is becoming increasingly difficult to maintain. We tend to relate computation capabilities with our ability to fit more transistors on a chip, but since that is becoming more difficult, other clever ways of continuing to expand computation power are becoming more of a focus, such as high performance and parallel computing.
What Is Extreme Ultra-Violet Lithography?
Extreme Ultra-Violet Lithography is a next-generation lithography technique which is expected to be used in high volumes by 2020. The technique uses the extreme ultra-violet wavelength (13.5 nm) to etch microchips that can have lines smaller than 0.1 microns. This process works by reflecting ultra-violet light from a pattern onto a silicon wafer and burning the design in.
Extreme Ultra-Violet Lithography. Image courtesy of Barret-Group.
The process, however, still suffers from issues with precision, which is highly reliant on the specialized mirrors being used to reflect the UV light. For example, tip-to-side gaps in bi-directional patterns remains the most difficult to print successfully.
Still, major semiconductor companies have been putting time and resources into developing the method, as it is still one of the most promising ways forward in the reduction of transistor size.
What Is 193 Immersion Lithography?
Immersion Lithography. Image courtesy of Controlled Environments Magazine.
193 Immersion Lithography is a technique to enhance photolithography resolution using a liquid medium as an immersion fluid that has a refractive index greater than 1 as a replacement for the air gap that usually exists between the lens and water surface. This can provide greater resolution for lithography that is equivalent to the refractive index.
In 193 Immersion Lithography in particular, a 193 nm wavelength of light is used for the etching process.
However, the process still faces challenges, including particle generation, water ionization, and liquid degassing.
Moore's Law still haunts the steps of chip makers, representing an increasingly difficult challenge to overcome. This work in the nanometer sphere requires new methods and materials. The coming year may bring smaller innovations yet, so stay tuned.