Fabless FPGA/eFPGA Players Ramp up Their Innovations—a Roundup
With products built on some of the most advanced semiconductor fab processes—like TSMC’s 7 nm node—fabless FPGA/eFPGA providers are rolling out new updated open-source tools, new devices, and new IP.
The fabless segment of the FPGA industry continues to offer interesting and innovative solutions for engineers, even as the larger fab-based FPGA players advance in practically their own separate worlds.
It’s these smaller, fabless FPGA technology providers that are driving the concept of embedded FPGAs (eFPGAs). eFPGAs function as blocks of FPGA IP functionality that can be integrated onto a system-on-chip (SoC) or ASIC.
In this article, we round up some of the latest products and innovations from these fabless FPGA/eFPGA companies, and we explore the trend toward flexibility in these advances.
Open-source Implemented Tools for eFPGAs
In keeping with the theme of flexibility, yesterday Quicklogic released a new version of its Aurora eFPGA development tool suite. According to the company, version 2.1 of its Aurora 2.1 suite is based on a fully open-source implementation. Support is provided for all major hardware description languages (HDLs), such as Verilog, System Verilog, and VHDL.
The Aurora 2.1 development tool suite is based on open source components allowing full code transparency. Image used courtesy of Quicklogic
The open-source components of the new Aurora version include the open-source synthesis (Yosys), Versatile Place and Route (VPR), and bitstream generation (OpenFPGA) software. Using the suite of tools, FPGA design engineers can go right from RTL to bitstream for Quicklogic's eFPGA IP.
Among the features is an architecture analysis mode. This mode lets users tune the architecture for their application, in contrast to being locked into a fixed-size tile approach. By using this feature, engineers can also make sure that their generated eFPGA IP is optimized in terms of how many logic (LUTs), BRAM, and DSP blocks are used so that they can meet their application requirements.
The open source nature of Quicklogic’s Aurora toolset has a number of benefits, according to the company. Because its code is open source, Aurora’s code can be inspected and improved by the development community.
This ensures flexibility as well, the argument being that publicly auditable code makes for higher quality software. Features are added based on merit, while still allowing the optional to add enhancements that are customer-specific. Quicklogic's Aurora 2.1 Development Tool Suite is available now.
Achronix FPGAs Target High-speed Designs
For its part, Achronix Semiconductor is a provider of both FPGAs and eFPGAs. Its latest offering is in the FPGA camp. In late December, the company announced the production release of its AC7t1500 FPGA. As part of the same announcement, the company also revealed that it’s added its power-efficient AC7t800 FPGA to the Achronix Tool Suite. The history of the Speedster7t FPGA family is notable in that it achieved first-pass silicon success when it was designed back in 2021.
Both FPGAs are part of the company’s high-end Speedster7t FPGA product family. These FPGAs are built on TSMC’s 7 nm process. The Speedster7t architecture includes a 20 Tbps 2D network-on-chip (2D NoC). This NoC enables high-speed interfacing between the FPGA’s fabric and the high-speed interface technologies, such as 400G Ethernet, PCIe Gen5, GDDR6 and DDR4/5. More information is available in the Speedster7t datasheet.
Overview of the Speedster7t FPGA family, with the newly available 7t15000 compared with the 7t800. Image used courtesy of Achronix Semiconductor
Another important aspect of Speedster7t FPGAs are their machine learning processors (MLPs). These MLPs are distributed across the FPGA fabric, with each MLP acting as a configurable, compute-intensive block. These MLPs sport up to 32 multipliers that support integer formats from 4- to 2- bits and various floating-point modes. This includes direct support for Tensorflow's bfloat16 ITALIC format and block floating-point (BFP) format.
According to the company, the Achronix Tool Suite suite comes with ACE design tools from Achronix and Synplify-Pro from Synopsys for the synthesis of FPGA designs. The Achronix simulation libraries are supported by ModelSim from Siemens EDA (formerly Mentor), VCS from Synopsys, and Riviera-PRO from Aldec. Standard RTL (VHDL and Verilog) input and industry-standard simulation are supported. The tool suite also includes a real-time design debugging tool called Snapshot Debugger.
eFPGA Ported to 7 nm Process
Unlike Quicklogic and Achronix, who both provide FPGAs and eFPGAs, Flex Logix Technologies is a company that focuses on eFPGAs, along with AI inference IP products. Last Fall the company announced the competition of porting its EFLX 4K eFPGA IP core—both the Logic and DSP versions—to TSMC’s 7 nm process. The IP was delivered to the product’s lead customer for integration into a production ASIC, says Flex Logix.
Now that this eFPGA IP technology is available in 7 nm with TSMC, engineers can develop devices using the IP that can be reconfigured after tape-out to adapt to new requirements, says the company. Engineers can reconfigure the device, changing standards and protocols as needed.
Thanks to its modular architecture, engineers can decide what mix of logic and DSP functionality they want in their eFPGA-based design. Image used courtesy of Flex Logix
Because the EFLX eFPGA is modular, arrays can be spread throughout the chip. These arrays can have all-logic or be heavy-DSP, and can integrate RAM in an array of many types, says the company. The 7 nm process support is the latest geometry for EFLX eFPGA family, which currently is also available on 12-, 16-, 22-, 28- and 40-nm process nodes. More information is available in the EFLX eFPGA product brief.