Achieve dramatic productivity and turnaround time improvements in early design electrical rule checking

White Paper Overview

Early-stage IC design layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows that require correct connectivity for valid results. The Calibre® nmLVS Recon™ tool targets essential and relevant early-stage circuit verification pain points, such as electrical rule checking (ERC) and soft connection checking (softchk), to enable designers to perform fast, efficient, and focused early-stage LVS runs.

In this white paper by Siemens, learn how the Calibre nmLVS Recon ERC and Softchk functions focus on improving turnaround time and simplifying debugging in early-stage iterations, leading to an overall reduction in tapeout schedules.