Gate drivers enable power switches to turn on and off faster, but as slew rates increase, there is also increased measurement and characterization uncertainty. Gate driver designers must account for accurate timing, controllable gate rise and fall times, and robustness against noise sources while minimizing noise coupling and parasitic inductance. Additionally, silicon-based power designs come with their own unique challenges.
This Rohde & Schwartz white paper describes key considerations when measuring and characterizing gate drivers, specifically covering the following items:
• Challenges and techniques presently used
• Techniques and considerations for measuring the high side gate driver
• Techniques and considerations for measuring the low side gate driver