Five key workflows that deliver 3D IC packaging success

White Paper Overview

The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SoC device can be mounted and interconnected in a single package using high speed/bandwidth chiplet-tochiplet interfaces. The resulting 3D IC heterogeneously integrated packages deliver greater performance at a reduced cost, higher yield, and have only a slightly larger area than a traditional monolithic SoC package.

This paper explores these new challenges and outlines five key workflows that address and manage them. These five workflows span several interlinked domain areas:

• Architecture definition
• Design activities (including planning, prototyping, system technology co-optimization, and detailed physical implementation of the substrates)
• Multi-physics analysis
• Device-level test
• Manufacturing