How Google and Intel use Calibre DesignEnhancer to Reduce IR drop and Improve Reliability

White Paper Overview

In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing power integrity and reducing IR drop. Calibre DE improves design reliability and manufacturability across multiple foundry technologies, reduces support costs and increases usability for foundries, CAD teams, and designers. Through real-world examples from Intel and Google, we highlight how Calibre DE maximizes layout modifications while ensuring DRC compliance. Intel’s use of the DE Via flow to insert additional vias for IR drop reduction showcases how detailed knowledge of design rules leads to significant improvements in power delivery.