Improving Productivity With More Efficient LVS Debug
White Paper Overview
Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SoC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor. Full-chip LVS runs not only to compare the design layout against the schematic netlist, but it also typically includes additional verification - such as electrical rule checking (ERC) and short isolation - that increase LVS runtimes.
In this white paper from Siemens Digital Industries Software, you'll learn more about the challenges of LVS debugging, interactive short isolation, comparison discrepancies, and more. Discover how Calibre RVE utilities help designers debug and fix LVS errors more quickly, while also eliminating the need for multiple full LVS runs.