Industry White Paper

Improving Productivity With More Efficient LVS Debug

July 30, 2020 by Mentor Graphics

Overview

Layout vs. schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SOC) design cycle. Yet with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor. Full-chip LVS runs not only compare the design layout against the schematic netlist, but also typically include additional verification, such as electrical rule checking (ERC) and short isolation, that increase LVS runtimes.

Debugging LVS results for these designs can be equally challenging and time-consuming depending on the complexity of the design, which can impact the overall turnaround time (TAT) and the planned tapeout schedule. Resolving shorts between power-ground nets can be difficult and time-consuming, due not only to the nature of these large nets with power-ground grids extending across the entire design size, but also because there can be many different causes for a short. Similarly, identifying comparison discrepancies between layout and schematic can be difficult, as there can be many causes for the discrepancies, and keeping track of corresponding elements in highly dense designs can be laborious. Implementing an effective and efficient methodology for LVS debug is crucial for designers who want to achieve LVS-clean results for their high-performance designs in the fastest closure time possible.

In this white paper by Mentor, a Siemens Business, learn more about LVS verification and explore how to improve productivity with more efficient LVS debug. 

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