Increase LVS Verification Productivity in Early Design Cycles

Whitepaper Overview

In today’s advanced integrated circuit (IC) design verification cycle, meeting planned deadlines in the quickest turnaround time (TAT) can be difficult, due to large design sizes, numerous hierarchies, and complex foundry decks. Layout vs. schematic (LVS) circuit verification is an essential stage of the design verification cycle, so tackling LVS verification issues and fixing them in an optimized approach can help designers meet their deadlines.

With the Calibre® nmLVS-Recon™ early verification tool, which enables design teams to rapidly examine unfinished designs to find and fix high-impact circuit errors earlier and faster, designers can run targeted short isolation analysis and debugging on blocks, macros and chips in early design phases. The Calibre nmLVS-Recon short isolation use model focuses on fast, efficient, prioritized short isolation and short paths debugging. 

In this whitepaper from Mentor, a Siemens Business, learn more about the supporting features of Calibre® nmLVS-Recon™ and how it can help increase productivity in early design cycles.