Integrated Hardened DSP on DAC/ADC ICs Improves Wideband Multichannel Systems

White Paper Overview

Over the past several decades, wireless system channel counts and bandwidths have steadily increased. The driving factors for these modern telecommunications, radar, and instrumentation systems are their data rate and overall system performance requirements. These requirements have also increased power envelopes and system complexities, making power density and component level features more important.

The semiconductor industry has integrated more channels on the same silicon footprint, reducing watt per channel requirements to help limitations. Additionally, semiconductor companies integrate more complex features into digital front ends that ease the off-chip hardware design historically achieved in an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA) fabric. These features can range from filters, downconverters, or numerically controlled oscillators (NCOs), to application-specific operations.

This white paper presents experimental results utilizing a 16-channel transmit and 16-channel receive subarray in which all transmit and receive channels are calibrated using hardened DSP blocks within the digitizer integrated circuit (IC). The resulting multichannel system provides performance improvements in size, weight, and power compared to other architectures. When comparing the resource utilization of an FPGA for the system, the hardened DSP blocks can solve significant challenges for designers of multichannel platforms.