Jitter Budgeting for Clock Distribution Networks in High-Speed PHYs and SerDes

White Paper Overview

High speed PHYs, such as industry’s recent DDR5/LPDDR5 operating at 6400 Mbps and high-speed SerDes, heavily rely on on-die clock distribution networks for clock and data transmission. Due to design sizes getting larger, long clock paths consisting of series of MOS clock buffers, e.g., CMOS or current-mode-logic (CML) buffers, are often necessary to enhance drivability.

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, N-cycle PSIJ and maximum time interval error (max. TIE) for MOS clock buffer chains experiencing sub-GHz power supply resonant variation. For single-tone power distribution network (PDN) ripple, the analytically estimated period PSIJ, N-cycle PSIJ and max. TIE achieve <5% error for low-hundred-ps latency buffer chains, and <15% error for otherwise longer latency buffer chains, when compared to SPICE simulated PSIJ and max. TIE. The jitter budgeting expression can be hand calculated and is practically precise for clock distribution networks in high-speed PHYs such as DDR and SerDes.