Microsoft Accelerates DRC for Advanced IC Designs with Shift-left Verification

Microsoft accelerates IC design verification with Siemens' Calibre nmDRC Recon, reducing runtimes by focusing on local checks earlier in the flow. This shift-left approach enhances productivity, simplifies debugging and cuts time-to-market.

White Paper Overview

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial runtime and resource bottlenecks. Siemens’ Calibre platform offers advanced solutions, like Calibre nmDRC Recon, that leverage a “shift-left” approach—moving verification steps earlier in the design process—to reduce debug time, manage incomplete data, and expedite the path to tape-out. This paper discusses the shift left approach and describes how Microsoft used Calibre nmDRC Recon to run DRC faster, with maximum check coverage and minimum compute hardware.

What you’ll learn:

• How Calibre nmDRC Recon enables early-stage, shift-left verification to reduce IC design runtimes and hardware requirements.

• How localized checks streamline debugging and accelerate design iterations.

• Why features like auto-waivers and split-deck runs make the DRC process more efficient.

• How Microsoft successfully reduced time-to-market and enhanced productivity using these methods.