Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs
The integration of multiple digital signal processing (DSP) blocks, wideband digital-to-analog converters (DACs), and wideband analog-to-digital converters (ADCs) within a single monolithic chip are enabling the offloading of FPGA resources. This allows for a smaller footprint, lower power, and increased channel count platforms that can sample at higher rates than previously achievable.
Along with this new capability comes novel multichip synchronization (MCS) algorithms within these integrated circuits (ICs), which allow users to achieve a known (deterministic) phase for all channels when powering the system or otherwise making software modifications to the system. This deterministic phase simplifies the broader system-level calibration algorithms needed to achieve the synchronization of all channels at the output or input to the front-end networks attached to these ICs.
In this paper, you will see results that demonstrate the capability of MCS algorithms while using a 16-channel receiver/ transmitter platform consisting of multiple digitizer ICs, clock sources, and digital interfaces.