Proposed standardization of chiplet models for heterogenous integration

White Paper Overview

With the economics of transistor scaling no longer universally applicable, the semiconductor industry faces an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions. What we see is the move to innovative packaging technologies to support system-scaling demands and achieve lower system cost. This is driving an emerging trend to disaggregate what typically would be implemented as a single homogeneous, system-on-chip (SoC) ASIC device into discrete, unpackaged ASIC devices, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several of these chiplet devices are mounted and interconnected into a single package using high speed/bandwidth interfaces to deliver monolithic or greater performance at reduced cost, higher yield, and lower power with only a slightly larger area than a heterogeneous integrated advanced package. 

In this paper, we propose a set of standardized chiplet models that include thermal, physical, mechanical, IO, behavioral, power, signal and power integrity, electrical properties, and test models, as well as documentation to facilitate the integration of the chiplets into a design.