Reducing IR and EM Issues With Automated Via Insertion

White Paper Overview

IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming and do not guarantee correct-by-construction vias.

This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias. The results show significant improvements in EM/IR results, including substantial reductions in current density violations.

This white paper also explains how the Calibre® YieldEnhancer PowerVia utility provides a “push-button” via set-up and insertion process, delivering an easy, automated flow that inserts additional correct-by-construction vias as needed to reduce IR drop and EM issues, and improves design performance and reliability. Additionally, this resource describes how Siemens EDA determines how the use of the PowerVia utility affects both design quality and tapeout schedules, by working with integrated circuit (IC) design companies to implement and evaluate the PowerVia solution in production designs.