FPGA Based Srdy-Drdy Library on Common Data-Transfer Protocol

Details
Created: December 22, 2009
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: ASIC proven, Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Description
The srdy-drdy library provides a group of components all built around a common data-transfer protocol. This protocol is used in datapath applications and provides bidirectional flow control.
Components in the library provide basic timing closure, clock domain crossing, basic and advanced buffering, and some arbitration and specialized components. The components in the library have been used in multiple successful tape-outs and FPGA designs.