It’s All About the Timing: 5G Brings Timing Synchronization Burdens

March 25, 2021 by Jake Hertz

Renesas has released three new ICs in its communication timing portfolio to help alleviate the burden of 5G timing constraints.

In the world of wireless communications, protocols are king. Still, wireless connectivity requires improvements in the underlying hardware to facilitate these protocols. 

5G is the most recent development in the field and has certainly brought with it new strains on the hardware—timing synchronization being amongst the most important. Now, manufacturers like Renesas are rolling out new communication timing devices to ameliorate some of these burdens


Jitter attenuator and radio synchronizer 

Renesas says that the new jitter attenuator and radio synchronizer can address the phase noise challenges of 5G applications. Image used courtesy of Renesas

FDD vs. TDD 

One of the most challenging aspects of designing a wireless protocol and infrastructure is figuring out how to avoid interference: when millions of people are communicating wirelessly at the same time, how do we stop their signals from interacting with one another? 

Historically there have been two solutions: isolate uplink and downlink signals in frequency or isolate them in time


FDD separates uplink and downlink in the spectral domain

FDD separates uplink and downlink in the spectral domain. Image used courtesy of Cable Free

The former is known as frequency division duplexing (FDD), where the uplink (transmitter) and downlink (receiver) signals are sent in totally different frequency bands such that there is no possibility of interference between the two. In FDD, the channel size for both uplink and downlink is the same.


TDD separates uplink and downlink in the time domain

TDD separates uplink and downlink in the time domain. Image used courtesy of Cable Free

The latter is known as time division duplexing (TDD), where the uplink and downlink signals are sent in the same frequency band but are separated in time. TDD alternates the transmission and reception of station data overtime to ensure that there is no interference between the two. 


A Shift to TDD and the Need for Synchronization 

Since 5G provides greater data rates than previous generations, developers will need to account for differences in downlink and uplink traffic

Historically, user downlink traffic has been significantly higher than uplink time, since people tend to download more than they upload. With higher data rates making way for applications like cloud computing and live streaming, however, uplink traffic is looking to surge with 5G. 


TDD can require synchronizations of about 1.5 μs

TDD can require synchronizations of about 1.5 μs. Image used courtesy of Ericcson

In order to support this change, the uplink and downlink spectrums must be highly flexible. Whereas FDD has fixed and defined frequency bands for uplink and downlink, TDD uses variable duration time slots for communication. TDD then allows network performance to be tailored to meet different needs. It also efficiently uses a frequency domain that FDD can’t tap into.

However, TDD puts a burden on 5G designers; to efficiently isolate signals in time, engineers must consider very precise and strict time synchronization. 


Renesas Focuses on 5G Timing 

Renesas is approaching this problem with three new ICs in its communication timing portfolio—all aimed at 5G. 

The first of the three ICs is the 8V19N850, which the company calls the "industry’s first fully-integrated 5G synchronization solution." The IC features a dual DPLL front-end architecture for any frequency translation.

Each DPLL offers programmable bandwidth and a digitally-controlled oscillator for real-time frequency/phase adjustments. The system has the ability to lock on to 1 pulse per second input signals within 100s. 


Simplified block diagram of the 8V19N850D

Simplified block diagram of the 8V19N850D. Image used courtesy of Renesas

The two other releases, the 8V19N880 and the 8V19N882, are classified as RF sampling clock generators and clock jitter attenuators, which focus on meeting timing requirements with respect to clock synchronization.

Renesas explains that these devices use a 2-stage PLL to generate high-precision clocks with a selected VCO. Achieving clock jitter as low as 74 fs RMS and supporting frequencies up to 3932 MHz (6 GHz with an external VCO), the ICs are said to be an effective solution for low-power, high-precision clock synchronization. 


All in the Timing 

5G introduces tighter timing constraints as TDD systems are increasingly used. While the rollout of 5G devices is still underway, it's likely that this higher-bandwidth protocol will heighten the demand for timing synchronization devices similar to these new Renesas ICs.