Using Synopsys Tools, Complex AI SoC Achieves Verification in 5 Weeks

At Hot Chips 2025, Rebellions announced its newest AI accelerator, the Rebel-Quad. It delivers up to 2,048 teraflops on 8-bit Floating Point (FP8) computation with 50% lower power draw, making it a more energy-efficient alternative to leading GPUs.

Rebel-Quad. Image (modified) used courtesy of Rebellions

Even more impressive is the rate at which this chip came to market. Using Synopsys' EDA tools, including hardware-assisted validation (HAV), Rebellions achieved full bring-up and performed a live demo just five weeks after the first silicon arrival. Rebellions made use of the on-premises and cloud-based Synopsis EDA tool set, including Synopsys VCS, ZeBu, Virtualizer, and the Verification Continuum to easily co-develop hardware and software and accelerate pre-silicon validation.

Block diagram of Synopsys EDA tools used by Rebellions. Image used courtesy of Rebellions

All About Circuits recently sat down with Tom De Schutter, Synopsys' SVP of product management, and Jinwook Oh, Rebellions' co-founder and CTO, to discuss Rebel-Quad's rapid development cycle.

Rebel-Quad Tackles AI Acceleration at Low Power

Rebel-Quad is Rebellions’ answer to high-performance AI acceleration with reduced power consumption. The company created the chip for deployment in frontier LLMs—the largest AI data centers now in development. The accelerator architecture is a four-homogeneous chiplet UCIe-advanced based system on chip (SoC) supporting 144 GB of eternal high bandwidth memory at 4 TB/s. 

“As AI datacenters grow in size, the processor and accelerator chips and software to drive them are getting more complex,” De Schutter said. “Customers are looking for ways to effectively deal with all this complexity. How do they make sure that they are not sacrificing time to market, while being able to verify and validate these chips at the pre-silicon stage?”

Rebel-Quad data center AI accelerator development timeline with Synopsys hardware-assisted verification EDA tools. Image used courtesy of Rebellions

Validation has always been a key factor in chip development. But with increasingly complex IC design, old validation practices may no longer cut it.

“The best way to get the performance on the CPU side is to use a virtual prototype. That's where Synopsys Virtualizer sits,” De Schutter said. “It has open-source virtual models for the Arm components. These connect that with their AI chip that runs on the Zebu emulator.”

De Schutter noted that Rebellions uses Arm IP for the CPU chiplets along with their own accelerator chiplets.

Rebellions Pushes Down Power Consumption

Power consumption is one of the gating functions of data center design and construction. Data centers in design right now are pushing into the gigawatt range. Power grids are not yet ready to supply so much power. At the very least, it takes considerable time to build out the infrastructure needed to deliver adequate power to remote data center build sites. Rebellions designed its new Rebel-Quad with this in mind. The chip uses half the power of an equivalent conventional AI GPU. 

“We want to provide a performant and energy-efficient solution in a rack scale,” said Oh. “By understanding the requirements and limitations of AI-dedicated data centers, we can provide the best, optimized solution for those environments.”

Enter Hardware-Assisted Validation

Low power consumption isn’t enough. Rebellions also wanted to bring the complex chip to market faster than was previously possible. This is where the Synopsys tools come into play.

“We prepared most of the software stack during the pre-silicon phase, which helped us go from first silicon to live demo in just five weeks,” said Oh. “That’s a major achievement. Even more impressive was how closely ZeBu’s performance predictions matched the actual silicon—98% accuracy.”

According to De Schutter, the Synopsys HAV covers not only computational verification but also factors such as power consumption. Synopsys HAV is showing 95% to 98% simulation accuracy when it comes to power.

Synopsys hardware-assisted validation flow. Image used courtesy of Synopsys

De Schutter explained that data-driven software optimization was used to ensure accurate modeling and validation. 

“The model was 98% correlated with real silicon, meaning that their predictions came true when they got to silicon. That was possible by having the hardware profile data and software profile data for the validation stage,” he said. “Basically you make sure that the clocks are fixed at a given ratio to real hardware. Then you can do a correlation: say, if the simulator runs 10 times slower than in real time, you factor using that parameter everywhere and you can predict the performance.”

Oh further expressed the importance of Synopsys HAV: “Validation is challenging, but ZeBu is a perfect platform for that. Its speed, capacity, and support from the Synopsys team made the emulation of this project successful.”