DDR5 Memory Interface: Signal Integrity Debugging and Compliance Testing

Industry Webinar

DDR5 Memory Interface: Signal Integrity Debugging and Compliance Testing

Guido Schulze Product Management, Rohde & Schwarz

ABOUT

Guido Schulze has more than 25 years of experience in high-speed digital testing. He began his career as an application engineer for Automated Test Equipment (ATE), working on emerging interfaces such as DDR, PCIe, and XAUI. For the past 15 years, he has worked as a product manager for the oscilloscope product division at Rohde & Schwarz in Munich, specializing in high-end oscilloscope models and their respective applications.

Johannes Ganzert Senior Application Engineer, Rohde & Schwarz

ABOUT

Johannes Ganzert is a Senior Applications Engineer for oscilloscopes at Rohde & Schwarz in Munich, Germany. After graduation from the Technical University of Munich, he joined Rohde & Schwarz as a Development Engineer for digital hardware and software. Over time, Johannes acquired a vast experience in RF and digital applications, particularly high-speed digital design and serial buses. He is an active participant in several standardization consortia such as the OPEN Alliance and USB-IF.

Webinar Overview

The integration of DDR SDRAM memories into your design can be a challenging task. The increasing data rates with DDR5 and LPDDR5 demand even more care for signal integrity, the lower supply voltage decrease design margin, and the higher density of electronic components cause more potential interferer sources.

Join us to discover innovative tests solutions for debugging error sources in your memory interface design and to verify margins and compliance to the respective DDR5 and LPDDR5 JEDED specifications.

In this webinar, we will discuss the most efficient Signal Integrity debug tools for DDR memory designs and demonstrate on a live DDR5 setup how to use them.

You will learn:

Key challenges in integrating DDR5 and LPDDR5 SDRAM into your design
Advanced signal integrity debug tools specifically for DDR memory interfaces
Practical techniques like Zone Triggering to isolate READ/WRITE bursts
How to optimize your DDR5/LPDDR5 interface for peak performance and reliability
Running Automated Compliance Tests to ensure your design meets JEDEC standards

AI / Neural Networks

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Digital Signal Processing

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