This webinar is intended for engineers who work on high-speed digital design and test. In particular, we will be focusing on PCIe Gen 3 interfaces. After an overview of PCIe technology, we will be discussing PCIe testing for compliance, protocol trigger and decode, and signal integrity debug purposes.
Starting with system interoperability verification, you will learn details on decoding, serial triggering, eye diagram testing, de-embedding, impedance control, and jitter analysis, which all can help to identify root causes when compliance tests fail. Practical examples and demonstrations illustrate PCIe testing made easy and reliable.