Gaussian Noise Generator for FPGAs

Gaussian Noise Generator for FPGAs


Category: Arithmetic Core

Created: August 07, 2014

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The Gaussian Noise Generator core generates white Gaussian noise of standard normal distribution, which can be used to measure BER to extremely low BER levels (~10-15). The core uses a 64-bit combined Tausworthe generator and an approximation of the inverse normal cumulative distribution function, which obtains a PDF that is Gaussian to up to 9.1σ.
The core was designed using synthesizable Verilog code and can be delivered as a soft-IP targeted for any FPGA device and ASIC technology. C/MATLAB models and corresponding test benches are also available.


- Period of generated noise sequence is about 2^176
- Random distribution in the range of ±9.1σ
- Noise is quantized to 16 bits with 5 bits of integer and11 bits of fraction
- Internal 64-bit uniform random number generator with configurable initial seeds
- Based on a piecewise polynomial approximation of the inverse normal cumulative distribution function
- High throughput, over 300 MHz clock rate and output sample rate in advanced FPGA
- Fully synchronous design using single clock
- Design optimized for Xilinx & Altera FPGA technology


- Communication system requiring accurate emulation of an AWGN channel
- Bit error rate measurement system

Synthesis results

- Device: Virtex-6 XC6VLX240T-2ff1156
- Number of occupied Slices: 97
- Number of RAMB36E1: 1
- Number of DSP48E1s: 2
- Maximum frequency: 311.8 MHz

- Device: Stratix IV GX EP4SGX230KF40C3
- Total LABs: 34
- M9K blocks: 2
- DSP block 18-bit elements: 4
- Maximum frequency: 376.8 MHz