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Category: Arithmetic Core IP Cores (98)

Digital Video Broadcasting (DVB-S2) LDPC Decoder

Introduction: From my thesis: Low-Density Parity Check (LDPC) coding is a form of error coding introduced by Gallager that can achieve performance…

License : LGPL
Language : Verilog

Verilog Fixed Point Math Library

n/a

License : LGPL
Language : Verilog

32-bit Pipelined 5x4Gbps CRC Generator

A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input…

License : GPL
Language : VHDL

Parallel Two Dimensional DCT in VHDL

NEW: 12 bit input MDCT version created by Emrah Yuce has been added to project downloads. Parallel synthesizable implementation of 2D DCT in VHDL.…

Language : VHDL

2D FHT - Two Dimensional Fast Hartley Transform

RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points. Presented algorithm is FHT with decimation in frequency…

License : LGPL
Language : Verilog

Configurable Cordic Core in Verilog

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included…

Language : Verilog

Configurable CRC Core in Verilog

n/a

License : LGPL
Language : Verilog

Configurable Parallel Scrambler Descrambler

This is a behavioral module for parallel scrambler/descrambler. There are RTL scrambler modules available, the purpose of this project is to built…

License : LGPL
Language : VHDL

CORDIC Algorithm Core for Iterations

The CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions…

License : GPL
Language : VHDL

CORDIC Arctangent for IQ Signals

Streaming atan function based on CORDIC algorithm. [angle, modulus] = cordic([I, Q]) angle = atan(Q/I) modulus = sqrt(I^2+Q^2) angle in range…

License : LGPL
Language : Verilog

CRCAHB

Arithmetic core originally created by: Cesar, Julio Fernandes, Felipe //// CRCAHB CORE BLOCK This file is part of the APB to I2C project…

License : LGPL
Language : Verilog

openFPU64 - Open Source Double Precision FPU

Free and open source double precision Floating Point Unit (FPU). The openFPU64 currently features: - double precision - Addition/Subtraction -…

License : GPL
Language : VHDL

Discrete Cosine Transform Core (DCT)

Recent advances in communications and networking technologies have made it possible that many applications use digital videos such as…

Double Precision Floating Point Unit IEEE-754 Compliant

n/a

License : LGPL
Language : Verilog

FT816 Floating Point Accelerator

07/06/2019 - Updated the square root core to allow restarting the calculation any time load is active. 06/14/2019 - Updates have been made to…

License : LGPL
Language : Verilog

Fixed-Point Pipelined Quadratic Polynomial

Quadratic_func is a fully pipelined quadratic polynomial that computes the relation y = ax^2 + bx + c. On each rising-edge of the clock (when en is…

License : GPL
Language : VHDL

Elliptic Curve Group Core

The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements…

License : LGPL
Language : Verilog

Fixed Point Arithmetic Modules Verilog

This project was started in order to create fixed point (Q format) arithmetic modules in verilog. What was created was a parameterized (specify…

License : LGPL
Language : Verilog

Efficient Floating Point Logarithm Unit for FPGAs

VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…

License : LGPL
Language : VHDL

32-bit Fixed Point Square Root (Recursive Algorithm)

VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…

License : LGPL
Language : VHDL