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Category: Memory Core IP Cores (44)

8/16/32 bit Configurable SDRAM Controller

Feature: • 8/16/32 Configurable SDRAM data width • Wish Bone compatible • Application clock and SDRAM clock can be async •…

License : GPL
Language : Verilog

DDR2-SDRAM Controller on Xilinx Spartan-3A

This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board Function After a Power on : ================== 1. Init-Sequenz for the…

License : LGPL
Language : VHDL

16-bit SDRAM Controller Chip for Wishbone Interface

This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip. When…

License : GPL
Language : Verilog

2Q Cache Strategy on VHDL

Overview I implemented 2Q cache strategy from paper "2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm" written…

License : LGPL
Language : VHDL

Asynchronous Wishbone Compatible SDRAM Controller

SUPERSEDED BY HPDMC. Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the…

License : GPL
Language : Verilog

BRSFmnCE FPGA Implementation

This module implements a synchronous FIFO using Block RAM resources such as those found in SRAM-based FPGAs. This module has been used in several…

License : LGPL
Language : Verilog

CF Interleaver with 2 Interleaving Memories

Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…

32-bit CFI Flash Controller IP

CFI flash controller IP. Provides two modes of operation - simple (Wishbone bus straight through to flash bus, essentially, but with 32-bit word…

License : LGPL
Language : Verilog

32-bit DDR SDRAM Controller Core

The ddr_sdr controls read and write access of a programmable logic device to a single 256 Mbit memory device. The 32-bit wide user interface…

Implementation of DDR3 SDRAM Controller for FPGAs (Controller Core)

This is a controller core for DDR3 SDRAM. Default configuration supports one 64 bit UDIMM or SO-DIMM Supports DIMM sizes of 1GB, 2GB, 4GB and 8GB…

License : LGPL
Language : Verilog

DDR2 mem controller for Digilent Genesys Board

n/a

License : LGPL
Language : Verilog

FAT32 File System Parser

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

Configurable Direct Mapped Cache Controller

This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable…

License : LGPL
Language : Verilog

DPSFmnCE FIFO for UARTs

This project provides a parameterizable synchronous FIFO which uses LUTs instead of Block RAMs for its memory. The FIFO can be parameterized in…

License : LGPL
Language : Verilog

High Performance Dynamic Memory Controller (HPDMC)

HPDMC is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications. Fast DDR SDRAM controller…

License : GPL
Language : Verilog

Functional RAM Simulation Models

The simu_mem project provides functional simulation models of commercially available RAMs. Advantages of the simu_mem models…

License : LGPL
Language : VHDL

Generic FIFO in VHDL

A very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers. Does not support Wishbone yet, but it's planned.

License : LGPL
Language : VHDL

Wishbone Wrapper for Xilinx Memory Interface Generator (MIG)

Two WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback…

License : LGPL
Language : Verilog

Generic Multi-purpose FIFOs in Verilog

Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are…

Language : Verilog

HSSDRC IP Core Configurable SDRAM Controller

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core…

Language : Other