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Introducing Calibre nmLVS-Recon
Feature: • 8/16/32 Configurable SDRAM data width • Wish Bone compatible • Application clock and SDRAM clock can be async •…
This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board Function After a Power on : ================== 1. Init-Sequenz for the…
This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip. When…
Overview I implemented 2Q cache strategy from paper "2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm" written…
SUPERSEDED BY HPDMC. Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the…
This module implements a synchronous FIFO using Block RAM resources such as those found in SRAM-based FPGAs. This module has been used in several…
Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…
CFI flash controller IP. Provides two modes of operation - simple (Wishbone bus straight through to flash bus, essentially, but with 32-bit word…
The ddr_sdr controls read and write access of a programmable logic device to a single 256 Mbit memory device. The 32-bit wide user interface…
This is a controller core for DDR3 SDRAM. Default configuration supports one 64 bit UDIMM or SO-DIMM Supports DIMM sizes of 1GB, 2GB, 4GB and 8GB…
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This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable…
This project provides a parameterizable synchronous FIFO which uses LUTs instead of Block RAMs for its memory. The FIFO can be parameterized in…
HPDMC is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications. Fast DDR SDRAM controller…
The simu_mem project provides functional simulation models of commercially available RAMs. Advantages of the simu_mem models…
A very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers. Does not support Wishbone yet, but it's planned.
Two WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback…
Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are…
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core…
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