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Category: Uncategorized IP Cores (143)

Configurator

This application parses a Verilog define file and presents a GUI to the user

License : LGPL
Language : Verilog

Gsc

Description of project.. Features - feature1 - feature1.1 -feature1.2 -feature2

License : GPL
Language : Verilog

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…

License : LGPL
Language : Verilog & VHDL

Advanced Debug Interface for Multi-device JTAG Chains

The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a…

License : LGPL
Language : Other

Library of Commonly Used Base Functions

About this core This is a collection of commonly used base functions, used in all of ASTRONs other cores. These source files can work in any…

License : LGPL
Language : VHDL

Ogg Vorbis Encoder/Decoder for Virtex-II Pro FPGA

Status I just started reading the Ogg Vorbis spec. and I'm seeing if other people are interested.

VHDL 8254 Timer Using Synchronous Processor Interface

a VHDL version of the Intel 8254 timer. Note: uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.…

Language : VHDL

16x2 LCD controller for Xilinx

Controller for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards. Features - 4-bit LCD data interface - One…

License : LGPL
Language : VHDL

2nd order Sigma-Delta DAC

Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.…

License : Others
Language : VHDL

An Alternative Oscilloscope (AlternaScope)

AlternaScope provides a cheap alternative to expensive oscilloscopes; Using a VGA display and a simple mouse interface, a user can use this scope…

Language : Verilog

VHDL 6532 RIOT (RAM-I/O-TIMER)

VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER) Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible. The…

License : Others
Language : VHDL

Artificial Intelligence System Using FGPA/ASIC

The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time…

License : Others
Language : VHDL

Adjustable Frequency Divider

Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…

License : LGPL
Language : Verilog

Programmable Sound Generator AY-3-8910 Compatible Module

This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.

License : GPL
Language : Verilog

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog

Simple backtracking 9x9 Sudoku Solver in Verilog

Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C…

License : BSD
Language : Verilog

BU PACMAN Game with Advanced Digital Design Using Verilog

This is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic…

License : GPL
Language : Verilog

BigCounter for Xilinx FGPA

Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic Features Designed for…

License : GPL
Language : VHDL

Boundaries: Glitch-free Clock Switch Circuit

This project is a collection of small designs involved with clock boundaries. The clock_switch designs are based on an eetimes article. The…

Language : Verilog

Computer Operating Properly : Watchdog Timer Module

The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two…

License : BSD
Language : Verilog