Avalon to Wishbone Bridge

Details
Category: Uncategorized
Created: January 15, 2016
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: B.4
License: LGPL
Description
AVALON/WISHBONE Bridge
This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one knows is the open source bus protocol (circumvents all patents).
This bridge supports the wishbone B4 version, i.e it supports the use of ready signal, which makes the wishbone a pipelined bus. Wishbone B3 was not pipelined, i.e it can't emit requests unless the previous one has completed.
The configurable parameters of this bridge are Address Width, Data Width, Tag Width and the Max_Outstanding_Reqs which sets the pipelinability (how many requests can be in flight) of the bridge.
The RTL comes with a home made uvm testbench which I tested on modelsim. Any bug reported w.r.t this uvm testbench will e highly appreciated.