Boundaries: Glitch-free Clock Switch Circuit

Boundaries: Glitch-free Clock Switch Circuit


Category: Uncategorized

Created: July 02, 2004

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: n/a


This project is a collection of small designs involved with clock boundaries.
The clock_switch designs are based on an eetimes article.
The bc_fifo_basic design is based on ideas from generic_fifo_dc_gray.


- debouncer: debounce a mechanical switch.
- clock_switch2_basic: select 1 of 2 clocks, no glitches.
- clock_switch3_basic: select 1 of 3 clocks, no glitches.
- clock_switch4_basic: select 1 of 4 clocks, no glitches.
- clock_switch8_basic: select 1 of 8 clocks, no glitches.
- oc_fifo_basic: a one-clock fifo
- bc_fifo_basic: a boundary-crossing fifo
- clock_detect: a clock-active detector
- arbiter: a simple parameterized round-robin arbiter
- random_ff: a ff simulation model for async boundaries


- None of these designs have been verified in silicon.