Or try an example search: 8 bit multiplier
Introducing Calibre nmLVS-Recon
microsemi用のAHBmaster.vhd…
The PCI IP core (PCI bridge) is a member of a family of open source cores. It is a bus bridge device between the WISHBONE SoC bus and the PCI local…
Overview This package involves a PCIe Scatter-Gather DMA engine for Virtex5 and Virtex6. The design implements MAC, Physical (Xilinx Hard and Soft…
This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio…
The PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple…
This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller. The external…
This is a advanced Memory Controller intended for embedded applications. Some of the features are: - SDRAM, SSRAM, FLASH, ROM and many other…
ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface. The ATA interface provides a simple interface…
pcie_mini IP core PCI-express to Wishbone Bridge for Xilinx FPGAs. Developer: Istvan Nagy, Bluechip Technology, 2011 Very often we want to make a…
pcie_vera_tb FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy…
The PCIe_DS_DMA core provides PCI Express controller for Xilinx HARD core for Virtex5, Virtex6, Spartan6, Artix 7 FPGA. Main features PCI Express…
This is a very simple PCI-target to Wishbone-master bridge. PCI-Target only, the bandwidth is quite low, fixed memory-image size (16MB), but it has…
Large electronic systems often use multiple supply voltages that must come up and go down in a specified order. Also, it must be made sure that the…
rs232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type of bus. Specifically, it lets the user…
“pic” is a soft core, programmable interrupt controller which can be used as an interface between peripheral interrupt lines and…
Wupper is designed by Nikhef (Amsterdam, The Netherlands) for the CERN ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory…
This proyect is designed to adapt either a host system, or a perypherical controller system to a scsi bus. Also the chip is a DMA controller for a…
A project aimed at providing a DSP/FPGA based development board. Testing has begun, so far Power supplies, DSP, FPGAs have been proven to be 100%…
The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly…
Overview LCD character display controller with Wishbone and memory mapped interfaces. It is compatible with the following parts: Sitronix ST7066U,…
Don't have an AAC account? Create one now.
Forgot your password? Click here.